25693e9e69
arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/fake_syscall.cc: arch/alpha/faults.cc: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/circlebuf.cc: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/cprintf.cc: base/cprintf.hh: base/fast_alloc.cc: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/exec_aout.h: base/loader/exec_ecoff.h: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/pollevent.cc: base/pollevent.hh: base/random.cc: base/random.hh: base/range.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/statistics.cc: base/statistics.hh: base/str.cc: base/trace.cc: base/trace.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/console.cc: dev/console.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/simple_disk.cc: dev/simple_disk.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: sim/debug.cc: sim/eventq.cc: sim/eventq.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/prog.cc: sim/prog.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_object.cc: sim/sim_object.hh: sim/sim_time.cc: sim/system.cc: sim/system.hh: sim/universe.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/tap/tap.cc: Make include paths explicit. --HG-- extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
140 lines
4 KiB
C++
140 lines
4 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEMTEST_HH__
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#define __MEMTEST_HH__
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#include "sim/sim_object.hh"
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#include "mem/mem_interface.hh"
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#include "mem/functional_mem/functional_memory.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "base/statistics.hh"
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#include "sim/sim_stats.hh"
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class MemTest : public BaseCPU
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{
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public:
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MemTest(const std::string &name,
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MemInterface *_cache_interface,
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FunctionalMemory *main_mem,
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FunctionalMemory *check_mem,
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unsigned _memorySize,
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unsigned _percentReads,
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unsigned _percentUncacheable,
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unsigned _maxReads,
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unsigned _progressInterval,
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Addr _traceAddr);
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// register statistics
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virtual void regStats();
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// main simulation loop (one cycle)
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void tick();
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protected:
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class TickEvent : public Event
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{
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private:
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MemTest *cpu;
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public:
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TickEvent(MemTest *c)
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: Event(&mainEventQueue, 100), cpu(c) {}
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void process() {cpu->tick();}
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virtual const char *description() { return "tick event"; }
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};
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TickEvent tickEvent;
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MemInterface *cacheInterface;
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FunctionalMemory *mainMem;
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FunctionalMemory *checkMem;
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ExecContext *xc;
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unsigned size; // size of testing memory region
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unsigned percentReads; // target percentage of read accesses
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unsigned percentUncacheable;
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Tick maxReads; // max # of reads to perform (then quit)
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unsigned blockSize;
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Addr blockAddrMask;
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Addr blockAddr(Addr addr)
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{
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return (addr & ~blockAddrMask);
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}
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Addr traceBlockAddr;
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Addr baseAddr1; // fix this to option
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Addr baseAddr2; // fix this to option
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Addr uncacheAddr;
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unsigned progressInterval; // frequency of progress reports
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Tick nextProgressMessage; // access # for next progress report
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Tick noResponseCycles;
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Statistics::Scalar<long long int> numReads;
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Statistics::Scalar<long long int> numWrites;
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Statistics::Scalar<long long int> numCopies;
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// called by MemCompleteEvent::process()
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void completeRequest(MemReqPtr req, uint8_t *data);
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friend class MemCompleteEvent;
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};
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class MemCompleteEvent : public Event
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{
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MemReqPtr req;
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uint8_t *data;
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MemTest *tester;
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public:
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MemCompleteEvent(MemReqPtr _req, uint8_t *_data, MemTest *_tester)
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: Event(&mainEventQueue),
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req(_req), data(_data), tester(_tester)
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{
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}
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void process();
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virtual const char *description();
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};
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#endif // __MEMTEST_HH__
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