841 lines
96 KiB
Plaintext
841 lines
96 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.541786 # Number of seconds simulated
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sim_ticks 541786101000 # Number of ticks simulated
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final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 115987 # Simulator instruction rate (inst/s)
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host_op_rate 142796 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 98087491 # Simulator tick rate (ticks/s)
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host_mem_usage 309428 # Number of bytes of host memory used
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host_seconds 5523.50 # Real time elapsed on the host
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sim_insts 640655084 # Number of instructions simulated
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sim_ops 788730743 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 18429184 # Number of bytes read from this memory
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system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 287956 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 303943 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 34015609 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 303943 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 34015609 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 290529 # Number of read requests accepted
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system.physmem.writeReqs 66098 # Number of write requests accepted
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system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 18289 # Per bank write bursts
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system.physmem.perBankRdBursts::1 18137 # Per bank write bursts
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system.physmem.perBankRdBursts::2 18222 # Per bank write bursts
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system.physmem.perBankRdBursts::3 18184 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18266 # Per bank write bursts
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system.physmem.perBankRdBursts::5 18308 # Per bank write bursts
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system.physmem.perBankRdBursts::6 18094 # Per bank write bursts
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system.physmem.perBankRdBursts::7 17914 # Per bank write bursts
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system.physmem.perBankRdBursts::8 17939 # Per bank write bursts
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system.physmem.perBankRdBursts::9 17962 # Per bank write bursts
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system.physmem.perBankRdBursts::10 18018 # Per bank write bursts
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system.physmem.perBankRdBursts::11 18110 # Per bank write bursts
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system.physmem.perBankRdBursts::12 18143 # Per bank write bursts
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system.physmem.perBankRdBursts::13 18270 # Per bank write bursts
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system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
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system.physmem.perBankRdBursts::15 18266 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4101 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4137 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4147 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4225 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4171 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4090 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4094 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4094 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 541786012500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 290529 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66098 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads
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system.physmem.totQLat 2707676000 # Total ticks spent queuing
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system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.33 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing
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system.physmem.readRowHits 194608 # Number of row buffer hits during reads
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system.physmem.writeRowHits 50098 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes
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system.physmem.avgGap 1519195.16 # Average gap between requests
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system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ)
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system.physmem_0.averagePower 693.117148 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 692.890615 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 156937341 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 673 # Number of system calls
|
|
system.cpu.numCycles 1083572202 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 640655084 # Number of instructions committed
|
|
system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.691350 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.591244 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 778221 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.645412 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999181 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 249632505 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 128813764 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 378446269 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 378446269 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 378446269 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 713747 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 137713 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 851460 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 851460 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 851460 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 23055853217 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9199211000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 32255064217 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 32255064217 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 250346252 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 379297729 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 379297729 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32302.557092 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66799.873650 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 91420 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 752 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68391 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 69143 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 69143 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712995 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 782317 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 782317 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21545578028 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4531082000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26076660028 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26076660028 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30218.413913 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65362.828539 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 23590 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 289921723 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 25342 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 480693746 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 480693746 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 480693746 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 480693746 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 480693746 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 480693746 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 289947065 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 289947065 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 289947065 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 289947065 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 289947065 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.263989 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 18968.263989 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25342 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 25342 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 25342 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.838371 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.838371 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 257749 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.519731 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 29632.926805 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002732 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.904325 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2800 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 22764 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 491102 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 513866 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 22764 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 494333 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 517097 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 22764 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 494333 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 517097 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2578 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 221893 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2578 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 287984 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 290562 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175909750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15921496500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4429448000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 175909750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 20350944500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 175909750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 20350944500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 25342 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 712995 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 25342 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 782317 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 807659 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 25342 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 782317 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 807659 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101728 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311213 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101728 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368117 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101728 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368117 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68234.968968 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71753.036373 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67020.441512 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 28 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2574 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221865 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 287956 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 287956 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143321250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13141995500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577310000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143321250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16719305500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143321250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16719305500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311173 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55680.361305 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59234.198724 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54127.036964 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1706737 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621824 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55919168 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 57540992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 899079 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 899079 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 224438 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 224438 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 66098 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 66091 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 66091 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 356627 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 356627 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|