810 lines
93 KiB
Text
810 lines
93 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.061494 # Number of seconds simulated
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sim_ticks 61493732000 # Number of ticks simulated
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final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 144123 # Simulator instruction rate (inst/s)
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host_op_rate 144840 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 97818525 # Simulator tick rate (ticks/s)
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host_mem_usage 433504 # Number of bytes of host memory used
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host_seconds 628.65 # Real time elapsed on the host
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sim_insts 90602849 # Number of instructions simulated
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sim_ops 91054080 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
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system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 806586 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 15403196 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 806586 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 15403196 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15575 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 993 # Per bank write bursts
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system.physmem.perBankRdBursts::1 890 # Per bank write bursts
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system.physmem.perBankRdBursts::2 949 # Per bank write bursts
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system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
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system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
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system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
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system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
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system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
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system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
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system.physmem.perBankRdBursts::9 962 # Per bank write bursts
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system.physmem.perBankRdBursts::10 938 # Per bank write bursts
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system.physmem.perBankRdBursts::11 899 # Per bank write bursts
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system.physmem.perBankRdBursts::12 904 # Per bank write bursts
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system.physmem.perBankRdBursts::13 867 # Per bank write bursts
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system.physmem.perBankRdBursts::14 877 # Per bank write bursts
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system.physmem.perBankRdBursts::15 905 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 61493643500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 15575 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation
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system.physmem.totQLat 73247750 # Total ticks spent queuing
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system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.13 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 14031 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 3948227.51 # Average gap between requests
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system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ)
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system.physmem_0.averagePower 671.483541 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ)
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system.physmem_1.averagePower 671.402933 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states
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system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.cpu.branchPred.lookups 20789429 # Number of BP lookups
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system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
|
system.cpu.numCycles 122987464 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 90602849 # Number of instructions committed
|
|
system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.357435 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.736684 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 946107 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.604238 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.882960 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 21598813 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4661073 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 26259886 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 26259886 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 26259886 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 914958 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 73908 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 988866 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 988866 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 988866 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11910296994 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2345727500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 14256024494 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 14256024494 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 22513771 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 27248752 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 27248752 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015609 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.036290 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.036290 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13017.315542 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31738.478920 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 943286 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11523 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27140 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 38663 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 38663 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9958855506 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1333449750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11292305256 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11292305256 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.322659 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28512.011418 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 5 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 27857009 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 27857009 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 27857009 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 803 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55346748 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 27857812 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 27857812 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 27857812 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 27857812 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 68924.966376 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53408252 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.415381 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.469913 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020612 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 935423 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 15583 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52344250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19360000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 958084250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 52344250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 977444250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 52344250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 977444250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967621 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967621 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967621 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67367.117117 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73893.129771 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65874.879675 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42469000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15862000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 774515250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42469000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 790377250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42469000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 790377250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.709677 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61960.937500 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53253.248762 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 1031 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 1031 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 15575 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 15575 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|