9e45ada171
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
1536 lines
174 KiB
Text
1536 lines
174 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 29197 # Simulator instruction rate (inst/s)
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host_mem_usage 217900 # Number of bytes of host memory used
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host_seconds 14.87 # Real time elapsed on the host
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host_tick_rate 14552660 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 434213 # Number of instructions simulated
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sim_seconds 0.000216 # Number of seconds simulated
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sim_ticks 216428500 # Number of ticks simulated
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system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu0.BPredUnit.BTBHits 44089 # Number of BTB hits
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system.cpu0.BPredUnit.BTBLookups 68668 # Number of BTB lookups
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system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu0.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect
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system.cpu0.BPredUnit.condPredicted 70848 # Number of conditional branches predicted
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system.cpu0.BPredUnit.lookups 70848 # Number of BP lookups
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system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu0.commit.COM:branches 23275 # Number of branches committed
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system.cpu0.commit.COM:bw_lim_events 180 # number cycles where commit BW limit reached
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system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu0.commit.COM:committed_per_cycle::samples 370366 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::mean 0.369578 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::stdev 0.675268 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::0 262900 70.98% 70.98% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::1 83158 22.45% 93.44% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::2 22390 6.05% 99.48% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::3 687 0.19% 99.67% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::4 335 0.09% 99.76% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::5 230 0.06% 99.82% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::6 452 0.12% 99.94% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::7 34 0.01% 99.95% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::8 180 0.05% 100.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::total 370366 # Number of insts commited each cycle
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system.cpu0.commit.COM:count 136879 # Number of instructions committed
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system.cpu0.commit.COM:loads 41762 # Number of loads committed
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system.cpu0.commit.COM:membars 84 # Number of memory barriers committed
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system.cpu0.commit.COM:refs 63149 # Number of memory references committed
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system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu0.commit.branchMispredicts 42322 # The number of times a branch was mispredicted
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system.cpu0.commit.commitCommittedInsts 136879 # The number of committed instructions
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system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
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system.cpu0.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit
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system.cpu0.committedInsts 116789 # Number of Instructions Simulated
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system.cpu0.committedInsts_total 116789 # Number of Instructions Simulated
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system.cpu0.cpi 3.706325 # CPI: Cycles Per Instruction
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system.cpu0.cpi_total 3.706325 # CPI: Total CPI of All Threads
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system.cpu0.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_avg_miss_latency 30381.703470 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency
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system.cpu0.dcache.ReadReq_hits 24348 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_latency 9631000 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_rate 0.012852 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_misses 317 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits
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system.cpu0.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
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system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_avg_miss_latency 15653.846154 # average SwapReq miss latency
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system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 12653.846154 # average SwapReq mshr miss latency
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system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits
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system.cpu0.dcache.SwapReq_miss_latency 407000 # number of SwapReq miss cycles
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system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses
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system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses
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system.cpu0.dcache.SwapReq_mshr_miss_latency 329000 # number of SwapReq MSHR miss cycles
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system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses
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system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses
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system.cpu0.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_avg_miss_latency 44931.354360 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36030.726257 # average WriteReq mshr miss latency
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system.cpu0.dcache.WriteReq_hits 20806 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_latency 24218000 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_rate 0.025252 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_misses 539 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_mshr_hits 360 # number of WriteReq MSHR hits
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system.cpu0.dcache.WriteReq_mshr_miss_latency 6449500 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_rate 0.008386 # mshr miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_mshr_misses 179 # number of WriteReq MSHR misses
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25250 # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.dcache.avg_refs 162.926136 # Average number of references to valid blocks.
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system.cpu0.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_mshrs 50500 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.demand_accesses 46010 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency 39543.224299 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency 29330.466830 # average overall mshr miss latency
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system.cpu0.dcache.demand_hits 45154 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 33849000 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_rate 0.018605 # miss rate for demand accesses
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system.cpu0.dcache.demand_misses 856 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 449 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.demand_mshr_miss_latency 11937500 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_rate 0.008846 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 407 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.occ_%::0 0.285120 # Average percentage of cache occupancy
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system.cpu0.dcache.occ_%::1 -0.014413 # Average percentage of cache occupancy
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system.cpu0.dcache.occ_blocks::0 145.981294 # Average occupied blocks per context
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system.cpu0.dcache.occ_blocks::1 -7.379294 # Average occupied blocks per context
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system.cpu0.dcache.overall_accesses 46010 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_avg_miss_latency 39543.224299 # average overall miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency 29330.466830 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_hits 45154 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 33849000 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_rate 0.018605 # miss rate for overall accesses
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system.cpu0.dcache.overall_misses 856 # number of overall misses
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system.cpu0.dcache.overall_mshr_hits 449 # number of overall MSHR hits
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system.cpu0.dcache.overall_mshr_miss_latency 11937500 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_rate 0.008846 # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_misses 407 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.replacements 10 # number of replacements
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system.cpu0.dcache.sampled_refs 176 # Sample count of references to valid blocks.
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system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.dcache.tagsinuse 138.602000 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 28675 # Total number of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.writebacks 6 # number of writebacks
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system.cpu0.decode.DECODE:BlockedCycles 52020 # Number of cycles decode is blocked
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system.cpu0.decode.DECODE:DecodedInsts 451824 # Number of instructions handled by decode
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system.cpu0.decode.DECODE:IdleCycles 163842 # Number of cycles decode is idle
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system.cpu0.decode.DECODE:RunCycles 154430 # Number of cycles decode is running
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system.cpu0.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing
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system.cpu0.decode.DECODE:UnblockCycles 74 # Number of cycles decode is unblocking
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system.cpu0.fetch.Branches 70848 # Number of branches that fetch encountered
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system.cpu0.fetch.CacheLines 87024 # Number of cache lines fetched
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system.cpu0.fetch.Cycles 242789 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu0.fetch.IcacheSquashes 20667 # Number of outstanding Icache misses that were squashed
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system.cpu0.fetch.Insts 457866 # Number of instructions fetch has processed
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system.cpu0.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing
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system.cpu0.fetch.branchRate 0.163675 # Number of branch fetches per cycle
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system.cpu0.fetch.icacheStallCycles 87024 # Number of cycles fetch is stalled on an Icache miss
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system.cpu0.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken
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system.cpu0.fetch.rate 1.057774 # Number of inst fetches per cycle
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system.cpu0.fetch.rateDist::samples 414658 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::mean 1.104202 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::stdev 2.128179 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::0 258930 62.44% 62.44% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::1 86799 20.93% 83.38% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::2 1004 0.24% 83.62% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::3 21052 5.08% 88.70% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::4 1074 0.26% 88.95% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::5 20905 5.04% 94.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::6 680 0.16% 94.16% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::7 710 0.17% 94.33% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::8 23504 5.67% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::total 414658 # Number of instructions fetched each cycle (Total)
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system.cpu0.icache.ReadReq_accesses 87024 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_avg_miss_latency 37020.114943 # average ReadReq miss latency
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency 35068.011958 # average ReadReq mshr miss latency
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system.cpu0.icache.ReadReq_hits 86154 # number of ReadReq hits
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system.cpu0.icache.ReadReq_miss_latency 32207500 # number of ReadReq miss cycles
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system.cpu0.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_misses 870 # number of ReadReq misses
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system.cpu0.icache.ReadReq_mshr_hits 201 # number of ReadReq MSHR hits
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system.cpu0.icache.ReadReq_mshr_miss_latency 23460500 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_rate 0.007688 # mshr miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_mshr_misses 669 # number of ReadReq MSHR misses
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system.cpu0.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.icache.avg_refs 128.973054 # Average number of references to valid blocks.
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system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.demand_accesses 87024 # number of demand (read+write) accesses
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system.cpu0.icache.demand_avg_miss_latency 37020.114943 # average overall miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency 35068.011958 # average overall mshr miss latency
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system.cpu0.icache.demand_hits 86154 # number of demand (read+write) hits
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system.cpu0.icache.demand_miss_latency 32207500 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_rate 0.009997 # miss rate for demand accesses
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system.cpu0.icache.demand_misses 870 # number of demand (read+write) misses
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system.cpu0.icache.demand_mshr_hits 201 # number of demand (read+write) MSHR hits
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system.cpu0.icache.demand_mshr_miss_latency 23460500 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_rate 0.007688 # mshr miss rate for demand accesses
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system.cpu0.icache.demand_mshr_misses 669 # number of demand (read+write) MSHR misses
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.occ_%::0 0.526858 # Average percentage of cache occupancy
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system.cpu0.icache.occ_blocks::0 269.751047 # Average occupied blocks per context
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|
system.cpu0.icache.overall_accesses 87024 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_avg_miss_latency 37020.114943 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency 35068.011958 # average overall mshr miss latency
|
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.icache.overall_hits 86154 # number of overall hits
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system.cpu0.icache.overall_miss_latency 32207500 # number of overall miss cycles
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system.cpu0.icache.overall_miss_rate 0.009997 # miss rate for overall accesses
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system.cpu0.icache.overall_misses 870 # number of overall misses
|
|
system.cpu0.icache.overall_mshr_hits 201 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_miss_latency 23460500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_rate 0.007688 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_misses 669 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
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system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.icache.replacements 363 # number of replacements
|
|
system.cpu0.icache.sampled_refs 668 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu0.icache.tagsinuse 269.751047 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 86154 # Total number of references to valid blocks.
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system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.writebacks 0 # number of writebacks
|
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system.cpu0.idleCycles 18200 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu0.iew.EXEC:branches 44503 # Number of branches executed
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|
system.cpu0.iew.EXEC:nop 59775 # number of nop insts executed
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system.cpu0.iew.EXEC:rate 0.436141 # Inst execution rate
|
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system.cpu0.iew.EXEC:refs 66647 # number of memory reference insts executed
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system.cpu0.iew.EXEC:stores 22312 # Number of stores executed
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system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu0.iew.WB:consumers 95172 # num instructions consuming a value
|
|
system.cpu0.iew.WB:count 187212 # cumulative count of insts written-back
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system.cpu0.iew.WB:fanout 0.972912 # average fanout of values written-back
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system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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|
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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|
system.cpu0.iew.WB:producers 92594 # num instructions producing a value
|
|
system.cpu0.iew.WB:rate 0.432502 # insts written-back per cycle
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|
system.cpu0.iew.WB:sent 187507 # cumulative count of insts sent to commit
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system.cpu0.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute
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system.cpu0.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
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system.cpu0.iew.iewDispLoadInsts 45739 # Number of dispatched load instructions
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system.cpu0.iew.iewDispNonSpecInsts 20652 # Number of dispatched non-speculative instructions
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|
system.cpu0.iew.iewDispSquashedInsts 2935 # Number of squashed instructions skipped by dispatch
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system.cpu0.iew.iewDispStoreInsts 43021 # Number of dispatched store instructions
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system.cpu0.iew.iewDispatchedInsts 316777 # Number of instructions dispatched to IQ
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system.cpu0.iew.iewExecLoadInsts 44335 # Number of load instructions executed
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system.cpu0.iew.iewExecSquashedInsts 42979 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.iewExecutedInsts 188787 # Number of executed instructions
|
|
system.cpu0.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread.0.memOrderViolation 197 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread.0.squashedLoads 3977 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread.0.squashedStores 21634 # Number of stores squashed
|
|
system.cpu0.iew.memOrderViolationEvents 197 # Number of memory order violations
|
|
system.cpu0.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.ipc 0.269809 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.269809 # IPC: Total IPC of All Threads
|
|
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.86% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.86% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.86% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.86% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.86% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.86% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.86% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::MemRead 44972 19.40% 90.27% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 22555 9.73% 100.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::total 231766 # Type of FU issued
|
|
system.cpu0.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested
|
|
system.cpu0.iq.ISSUE:fu_busy_rate 0.000574 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IntAlu 38 28.57% 28.57% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 28.57% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 28.57% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 28.57% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 28.57% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 28.57% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 28.57% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 28.57% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 28.57% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::MemRead 27 20.30% 48.87% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::samples 414658 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.558933 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.948995 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::0 280664 67.69% 67.69% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::1 66211 15.97% 83.65% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::2 42876 10.34% 93.99% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::3 21783 5.25% 99.25% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::4 1770 0.43% 99.67% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::5 925 0.22% 99.90% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::6 280 0.07% 99.96% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::7 123 0.03% 99.99% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::total 414658 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:rate 0.535432 # Inst issue rate
|
|
system.cpu0.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqInstsIssued 231766 # Number of instructions issued
|
|
system.cpu0.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqSquashedInstsExamined 98222 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.memDep0.conflictingLoads 19721 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 107 # Number of conflicting stores.
|
|
system.cpu0.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.numCycles 432858 # number of cpu cycles simulated
|
|
system.cpu0.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking
|
|
system.cpu0.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed
|
|
system.cpu0.rename.RENAME:IdleCycles 185237 # Number of cycles rename is idle
|
|
system.cpu0.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full
|
|
system.cpu0.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename
|
|
system.cpu0.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RENAME:RunCycles 133140 # Number of cycles rename is running
|
|
system.cpu0.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing
|
|
system.cpu0.rename.RENAME:UnblockCycles 353 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.RENAME:serializeStallCycles 51604 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed
|
|
system.cpu0.rename.RENAME:skidInsts 83212 # count of insts added to the skid buffer
|
|
system.cpu0.rename.RENAME:tempSerializingInsts 20768 # count of temporary serializing insts renamed
|
|
system.cpu0.timesIdled 340 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.BPredUnit.BTBHits 53713 # Number of BTB hits
|
|
system.cpu1.BPredUnit.BTBLookups 65870 # Number of BTB lookups
|
|
system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
system.cpu1.BPredUnit.condIncorrect 29792 # Number of conditional branches incorrect
|
|
system.cpu1.BPredUnit.condPredicted 83669 # Number of conditional branches predicted
|
|
system.cpu1.BPredUnit.lookups 83669 # Number of BP lookups
|
|
system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
|
system.cpu1.commit.COM:branches 25470 # Number of branches committed
|
|
system.cpu1.commit.COM:bw_lim_events 577 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.commit.COM:committed_per_cycle::samples 350132 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::mean 0.363609 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::stdev 0.831936 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::0 266836 76.21% 76.21% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::1 54270 15.50% 91.71% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::2 24066 6.87% 98.58% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::3 1288 0.37% 98.95% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::4 810 0.23% 99.18% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::5 561 0.16% 99.34% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::6 1684 0.48% 99.82% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::7 40 0.01% 99.84% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::8 577 0.16% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::total 350132 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:count 127311 # Number of instructions committed
|
|
system.cpu1.commit.COM:loads 29520 # Number of loads committed
|
|
system.cpu1.commit.COM:membars 8970 # Number of memory barriers committed
|
|
system.cpu1.commit.COM:refs 40059 # Number of memory references committed
|
|
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.branchMispredicts 29792 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.commitCommittedInsts 127311 # The number of committed instructions
|
|
system.cpu1.commit.commitNonSpecStalls 9688 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit
|
|
system.cpu1.committedInsts 102085 # Number of Instructions Simulated
|
|
system.cpu1.committedInsts_total 102085 # Number of Instructions Simulated
|
|
system.cpu1.cpi 3.872714 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 3.872714 # CPI: Total CPI of All Threads
|
|
system.cpu1.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_hits 28662 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_miss_latency 3852000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_rate 0.007067 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_misses 204 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency 2921500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate 0.006062 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency 22155.172414 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 24152.173913 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_miss_latency 1285000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_misses 58 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_mshr_hits 12 # number of SwapReq MSHR hits
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency 1111000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate 0.638889 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_accesses 10467 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency 23593.023256 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15414.414414 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_hits 10338 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_miss_latency 3043500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_rate 0.012324 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_misses 129 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency 1711000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate 0.010605 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_misses 111 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_refs 701.333333 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.demand_accesses 39333 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_avg_miss_latency 20707.207207 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_hits 39000 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_miss_latency 6895500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_rate 0.008466 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_misses 333 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_miss_latency 4632500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_rate 0.007271 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_misses 286 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.occ_%::0 0.053273 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_%::1 -0.013192 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_blocks::0 27.275525 # Average occupied blocks per context
|
|
system.cpu1.dcache.occ_blocks::1 -6.754298 # Average occupied blocks per context
|
|
system.cpu1.dcache.overall_accesses 39333 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_hits 39000 # number of overall hits
|
|
system.cpu1.dcache.overall_miss_latency 6895500 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_rate 0.008466 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_misses 333 # number of overall misses
|
|
system.cpu1.dcache.overall_mshr_hits 47 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_miss_latency 4632500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_rate 0.007271 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_misses 286 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.replacements 2 # number of replacements
|
|
system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.dcache.tagsinuse 20.521228 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 21040 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.writebacks 1 # number of writebacks
|
|
system.cpu1.decode.DECODE:BlockedCycles 30059 # Number of cycles decode is blocked
|
|
system.cpu1.decode.DECODE:DecodedInsts 353088 # Number of instructions handled by decode
|
|
system.cpu1.decode.DECODE:IdleCycles 174967 # Number of cycles decode is idle
|
|
system.cpu1.decode.DECODE:RunCycles 144955 # Number of cycles decode is running
|
|
system.cpu1.decode.DECODE:SquashCycles 33628 # Number of cycles decode is squashing
|
|
system.cpu1.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking
|
|
system.cpu1.fetch.Branches 83669 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.CacheLines 82467 # Number of cache lines fetched
|
|
system.cpu1.fetch.Cycles 239936 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.Insts 410532 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.branchRate 0.211635 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.rate 1.038412 # Number of inst fetches per cycle
|
|
system.cpu1.fetch.rateDist::samples 392437 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.046109 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 1.946317 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 234991 59.88% 59.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 84908 21.64% 81.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 20175 5.14% 86.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 13313 3.39% 90.05% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 2697 0.69% 90.74% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 17066 4.35% 95.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1329 0.34% 95.42% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 2421 0.62% 96.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 15537 3.96% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 392437 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_hits 81734 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_miss_latency 10621000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_rate 0.008888 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_misses 733 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate 0.007712 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_misses 636 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_refs 128.512579 # Average number of references to valid blocks.
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.demand_accesses 82467 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_avg_miss_latency 14489.768076 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_hits 81734 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_miss_latency 10621000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_rate 0.008888 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_misses 733 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_miss_latency 7591000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_rate 0.007712 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_misses 636 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.occ_%::0 0.183206 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_blocks::0 93.801528 # Average occupied blocks per context
|
|
system.cpu1.icache.overall_accesses 82467 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_hits 81734 # number of overall hits
|
|
system.cpu1.icache.overall_miss_latency 10621000 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_rate 0.008888 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_misses 733 # number of overall misses
|
|
system.cpu1.icache.overall_mshr_hits 97 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_miss_latency 7591000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_rate 0.007712 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_misses 636 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.icache.replacements 524 # number of replacements
|
|
system.cpu1.icache.sampled_refs 636 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.icache.tagsinuse 93.801528 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 81734 # Total number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.writebacks 0 # number of writebacks
|
|
system.cpu1.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.iew.EXEC:branches 36547 # Number of branches executed
|
|
system.cpu1.iew.EXEC:nop 47873 # number of nop insts executed
|
|
system.cpu1.iew.EXEC:rate 0.410671 # Inst execution rate
|
|
system.cpu1.iew.EXEC:refs 47615 # number of memory reference insts executed
|
|
system.cpu1.iew.EXEC:stores 12164 # Number of stores executed
|
|
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu1.iew.WB:consumers 78764 # num instructions consuming a value
|
|
system.cpu1.iew.WB:count 158732 # cumulative count of insts written-back
|
|
system.cpu1.iew.WB:fanout 0.929676 # average fanout of values written-back
|
|
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.iew.WB:producers 73225 # num instructions producing a value
|
|
system.cpu1.iew.WB:rate 0.401501 # insts written-back per cycle
|
|
system.cpu1.iew.WB:sent 158983 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewDispLoadInsts 39543 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 8501 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewDispSquashedInsts 3508 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispStoreInsts 20654 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispatchedInsts 261662 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewExecLoadInsts 35451 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 33572 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.iewExecutedInsts 162357 # Number of executed instructions
|
|
system.cpu1.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.iewSquashCycles 33628 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.lsq.thread.0.forwLoads 6568 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread.0.memOrderViolation 694 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread.0.squashedLoads 10023 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread.0.squashedStores 10115 # Number of stores squashed
|
|
system.cpu1.iew.memOrderViolationEvents 694 # Number of memory order violations
|
|
system.cpu1.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.ipc 0.258217 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.258217 # IPC: Total IPC of All Threads
|
|
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.15% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.15% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.15% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.15% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.15% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.15% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.15% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::MemRead 45623 23.29% 93.43% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 12865 6.57% 100.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::total 195929 # Type of FU issued
|
|
system.cpu1.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested
|
|
system.cpu1.iq.ISSUE:fu_busy_rate 0.000949 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::samples 392437 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.499262 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.956261 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::0 275791 70.28% 70.28% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::1 71375 18.19% 88.46% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::2 23368 5.95% 94.42% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::3 13587 3.46% 97.88% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::4 5437 1.39% 99.27% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::5 2194 0.56% 99.83% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::6 490 0.12% 99.95% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::total 392437 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:rate 0.495589 # Inst issue rate
|
|
system.cpu1.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqInstsIssued 195929 # Number of instructions issued
|
|
system.cpu1.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqSquashedInstsExamined 74909 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 7843 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.iqSquashedOperandsExamined 33478 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.memDep0.conflictingLoads 6760 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 87 # Number of conflicting stores.
|
|
system.cpu1.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.numCycles 395346 # number of cpu cycles simulated
|
|
system.cpu1.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed
|
|
system.cpu1.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle
|
|
system.cpu1.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.RENAME:RenameLookups 447878 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.RENAME:RenamedInsts 290237 # Number of instructions processed by rename
|
|
system.cpu1.rename.RENAME:RenamedOperands 204758 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RENAME:RunCycles 133245 # Number of cycles rename is running
|
|
system.cpu1.rename.RENAME:SquashCycles 33628 # Number of cycles rename is squashing
|
|
system.cpu1.rename.RENAME:UnblockCycles 630 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RENAME:UndoneMaps 119564 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.RENAME:serializeStallCycles 29341 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RENAME:serializingInsts 8772 # count of serializing insts renamed
|
|
system.cpu1.rename.RENAME:skidInsts 33179 # count of insts added to the skid buffer
|
|
system.cpu1.rename.RENAME:tempSerializingInsts 8900 # count of temporary serializing insts renamed
|
|
system.cpu1.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.BPredUnit.BTBHits 52073 # Number of BTB hits
|
|
system.cpu2.BPredUnit.BTBLookups 66680 # Number of BTB lookups
|
|
system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
system.cpu2.BPredUnit.condIncorrect 30422 # Number of conditional branches incorrect
|
|
system.cpu2.BPredUnit.condPredicted 81408 # Number of conditional branches predicted
|
|
system.cpu2.BPredUnit.lookups 81408 # Number of BP lookups
|
|
system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
|
system.cpu2.commit.COM:branches 25190 # Number of branches committed
|
|
system.cpu2.commit.COM:bw_lim_events 578 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.commit.COM:committed_per_cycle::samples 347008 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::mean 0.368821 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::stdev 0.833965 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::0 262750 75.72% 75.72% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::1 55494 15.99% 91.71% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::2 23803 6.86% 98.57% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::3 1293 0.37% 98.94% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::4 820 0.24% 99.18% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::5 559 0.16% 99.34% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::6 1671 0.48% 99.82% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::7 40 0.01% 99.83% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::8 578 0.17% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::total 347008 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:count 127984 # Number of instructions committed
|
|
system.cpu2.commit.COM:loads 30137 # Number of loads committed
|
|
system.cpu2.commit.COM:membars 7796 # Number of memory barriers committed
|
|
system.cpu2.commit.COM:refs 41570 # Number of memory references committed
|
|
system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.branchMispredicts 30422 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.commitCommittedInsts 127984 # The number of committed instructions
|
|
system.cpu2.commit.commitNonSpecStalls 8513 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit
|
|
system.cpu2.committedInsts 104211 # Number of Instructions Simulated
|
|
system.cpu2.committedInsts_total 104211 # Number of Instructions Simulated
|
|
system.cpu2.cpi 3.790608 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 3.790608 # CPI: Total CPI of All Threads
|
|
system.cpu2.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_hits 28373 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_miss_latency 4031500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_rate 0.007312 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_misses 209 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency 3023000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate 0.006088 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency 21973.684211 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 23510.869565 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_hits 14 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_miss_latency 1252500 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_misses 57 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency 1081500 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate 0.647887 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_accesses 11362 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency 24003.906250 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15831.818182 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_hits 11234 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_miss_latency 3072500 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_rate 0.011266 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_misses 128 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency 1741500 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009681 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_misses 110 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_refs 708.483871 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.demand_accesses 39944 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_avg_miss_latency 21080.118694 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_hits 39607 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_miss_latency 7104000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_rate 0.008437 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_misses 337 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.demand_mshr_miss_latency 4764500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_rate 0.007110 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_misses 284 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dcache.occ_%::0 0.057032 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.occ_%::1 -0.010468 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.occ_blocks::0 29.200191 # Average occupied blocks per context
|
|
system.cpu2.dcache.occ_blocks::1 -5.359479 # Average occupied blocks per context
|
|
system.cpu2.dcache.overall_accesses 39944 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu2.dcache.overall_hits 39607 # number of overall hits
|
|
system.cpu2.dcache.overall_miss_latency 7104000 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_rate 0.008437 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_misses 337 # number of overall misses
|
|
system.cpu2.dcache.overall_mshr_hits 53 # number of overall MSHR hits
|
|
system.cpu2.dcache.overall_mshr_miss_latency 4764500 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_rate 0.007110 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_misses 284 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu2.dcache.replacements 2 # number of replacements
|
|
system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu2.dcache.tagsinuse 23.840712 # Cycle average of tags in use
|
|
system.cpu2.dcache.total_refs 21963 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.writebacks 1 # number of writebacks
|
|
system.cpu2.decode.DECODE:BlockedCycles 31861 # Number of cycles decode is blocked
|
|
system.cpu2.decode.DECODE:DecodedInsts 361505 # Number of instructions handled by decode
|
|
system.cpu2.decode.DECODE:IdleCycles 170760 # Number of cycles decode is idle
|
|
system.cpu2.decode.DECODE:RunCycles 144226 # Number of cycles decode is running
|
|
system.cpu2.decode.DECODE:SquashCycles 34255 # Number of cycles decode is squashing
|
|
system.cpu2.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking
|
|
system.cpu2.fetch.Branches 81408 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.CacheLines 81347 # Number of cache lines fetched
|
|
system.cpu2.fetch.Cycles 236913 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.Insts 412447 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.branchRate 0.206084 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.rate 1.044109 # Number of inst fetches per cycle
|
|
system.cpu2.fetch.rateDist::samples 389876 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.057893 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 1.974904 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 234334 60.10% 60.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 83865 21.51% 81.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 17837 4.58% 86.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 14411 3.70% 89.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 2742 0.70% 90.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 1358 0.35% 95.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 2423 0.62% 95.80% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 16356 4.20% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 389876 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_hits 80599 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_miss_latency 14184500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_rate 0.009195 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_misses 748 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_mshr_hits 116 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency 10114500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate 0.007769 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_misses 632 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_refs 127.530063 # Average number of references to valid blocks.
|
|
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.demand_accesses 81347 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_avg_miss_latency 18963.235294 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_hits 80599 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_miss_latency 14184500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_rate 0.009195 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_misses 748 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_mshr_hits 116 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.demand_mshr_miss_latency 10114500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_rate 0.007769 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_misses 632 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.icache.occ_%::0 0.191472 # Average percentage of cache occupancy
|
|
system.cpu2.icache.occ_blocks::0 98.033912 # Average occupied blocks per context
|
|
system.cpu2.icache.overall_accesses 81347 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu2.icache.overall_hits 80599 # number of overall hits
|
|
system.cpu2.icache.overall_miss_latency 14184500 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_rate 0.009195 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_misses 748 # number of overall misses
|
|
system.cpu2.icache.overall_mshr_hits 116 # number of overall MSHR hits
|
|
system.cpu2.icache.overall_mshr_miss_latency 10114500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_rate 0.007769 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_misses 632 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu2.icache.replacements 522 # number of replacements
|
|
system.cpu2.icache.sampled_refs 632 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu2.icache.tagsinuse 98.033912 # Cycle average of tags in use
|
|
system.cpu2.icache.total_refs 80599 # Total number of references to valid blocks.
|
|
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.writebacks 0 # number of writebacks
|
|
system.cpu2.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.iew.EXEC:branches 37149 # Number of branches executed
|
|
system.cpu2.iew.EXEC:nop 47058 # number of nop insts executed
|
|
system.cpu2.iew.EXEC:rate 0.419988 # Inst execution rate
|
|
system.cpu2.iew.EXEC:refs 49104 # number of memory reference insts executed
|
|
system.cpu2.iew.EXEC:stores 13043 # Number of stores executed
|
|
system.cpu2.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu2.iew.WB:consumers 81150 # num instructions consuming a value
|
|
system.cpu2.iew.WB:count 162295 # cumulative count of insts written-back
|
|
system.cpu2.iew.WB:fanout 0.931855 # average fanout of values written-back
|
|
system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.iew.WB:producers 75620 # num instructions producing a value
|
|
system.cpu2.iew.WB:rate 0.410849 # insts written-back per cycle
|
|
system.cpu2.iew.WB:sent 162544 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewDispLoadInsts 40176 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 9384 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewDispSquashedInsts 3614 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispStoreInsts 22433 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispatchedInsts 266034 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewExecLoadInsts 36061 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 34221 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.iewExecutedInsts 165905 # Number of executed instructions
|
|
system.cpu2.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.iewSquashCycles 34255 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.lsq.thread.0.forwLoads 7459 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread.0.memOrderViolation 698 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread.0.squashedLoads 10039 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread.0.squashedStores 11000 # Number of stores squashed
|
|
system.cpu2.iew.memOrderViolationEvents 698 # Number of memory order violations
|
|
system.cpu2.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.ipc 0.263810 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.263810 # IPC: Total IPC of All Threads
|
|
system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.63% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.63% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.63% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.63% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.63% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.63% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.63% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::MemRead 45052 22.51% 93.14% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::MemWrite 13735 6.86% 100.00% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::total 200126 # Type of FU issued
|
|
system.cpu2.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested
|
|
system.cpu2.iq.ISSUE:fu_busy_rate 0.000904 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::IntAlu 19 10.50% 10.50% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 10.50% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.50% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.50% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.50% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.50% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.50% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.50% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.50% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::MemRead 17 9.39% 19.89% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::samples 389876 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.513307 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.969448 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::0 272512 69.90% 69.90% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::1 69416 17.80% 87.70% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::2 25173 6.46% 94.16% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::3 14490 3.72% 97.87% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::4 5424 1.39% 99.27% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::5 2186 0.56% 99.83% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::6 485 0.12% 99.95% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::7 162 0.04% 99.99% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::8 28 0.01% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::total 389876 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:rate 0.506619 # Inst issue rate
|
|
system.cpu2.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqInstsIssued 200126 # Number of instructions issued
|
|
system.cpu2.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqSquashedInstsExamined 77302 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 8735 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.iqSquashedOperandsExamined 33615 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.memDep0.conflictingLoads 7669 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 92 # Number of conflicting stores.
|
|
system.cpu2.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.numCycles 395023 # number of cpu cycles simulated
|
|
system.cpu2.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed
|
|
system.cpu2.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle
|
|
system.cpu2.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.RENAME:RenamedInsts 293451 # Number of instructions processed by rename
|
|
system.cpu2.rename.RENAME:RenamedOperands 211386 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RENAME:RunCycles 131636 # Number of cycles rename is running
|
|
system.cpu2.rename.RENAME:SquashCycles 34255 # Number of cycles rename is squashing
|
|
system.cpu2.rename.RENAME:UnblockCycles 645 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RENAME:UndoneMaps 123786 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.RENAME:serializeStallCycles 31130 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RENAME:serializingInsts 9653 # count of serializing insts renamed
|
|
system.cpu2.rename.RENAME:skidInsts 36749 # count of insts added to the skid buffer
|
|
system.cpu2.rename.RENAME:tempSerializingInsts 9784 # count of temporary serializing insts renamed
|
|
system.cpu2.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu3.BPredUnit.BTBHits 48405 # Number of BTB hits
|
|
system.cpu3.BPredUnit.BTBLookups 65841 # Number of BTB lookups
|
|
system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
system.cpu3.BPredUnit.condIncorrect 32660 # Number of conditional branches incorrect
|
|
system.cpu3.BPredUnit.condPredicted 82266 # Number of conditional branches predicted
|
|
system.cpu3.BPredUnit.lookups 82266 # Number of BP lookups
|
|
system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
|
system.cpu3.commit.COM:branches 25082 # Number of branches committed
|
|
system.cpu3.commit.COM:bw_lim_events 576 # number cycles where commit BW limit reached
|
|
system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu3.commit.COM:committed_per_cycle::samples 346536 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::mean 0.381828 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::stdev 0.836481 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::0 257870 74.41% 74.41% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::1 60023 17.32% 91.73% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::2 23680 6.83% 98.57% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::3 1288 0.37% 98.94% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::4 802 0.23% 99.17% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::5 567 0.16% 99.33% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::6 1691 0.49% 99.82% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::7 39 0.01% 99.83% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::8 576 0.17% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::total 346536 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:count 132317 # Number of instructions committed
|
|
system.cpu3.commit.COM:loads 32415 # Number of loads committed
|
|
system.cpu3.commit.COM:membars 5314 # Number of memory barriers committed
|
|
system.cpu3.commit.COM:refs 46218 # Number of memory references committed
|
|
system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu3.commit.branchMispredicts 32660 # The number of times a branch was mispredicted
|
|
system.cpu3.commit.commitCommittedInsts 132317 # The number of committed instructions
|
|
system.cpu3.commit.commitNonSpecStalls 6025 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu3.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit
|
|
system.cpu3.committedInsts 111128 # Number of Instructions Simulated
|
|
system.cpu3.committedInsts_total 111128 # Number of Instructions Simulated
|
|
system.cpu3.cpi 3.551805 # CPI: Cycles Per Instruction
|
|
system.cpu3.cpi_total 3.551805 # CPI: Total CPI of All Threads
|
|
system.cpu3.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_hits 28295 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_miss_latency 3169000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_rate 0.006670 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_misses 190 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency 2299000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate 0.005441 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency 22773.584906 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22782.608696 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_hits 12 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_miss_latency 1207000 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_rate 0.815385 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_misses 53 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_mshr_hits 7 # number of SwapReq MSHR hits
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency 1048000 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate 0.707692 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_accesses 13738 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency 22585.271318 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14535.714286 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_hits 13609 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_miss_latency 2913500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_rate 0.009390 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_misses 129 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency 1628000 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate 0.008153 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_misses 112 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_refs 810.166667 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.demand_accesses 42223 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_avg_miss_latency 19067.398119 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_hits 41904 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_miss_latency 6082500 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_rate 0.007555 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_misses 319 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.demand_mshr_miss_latency 3927000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_rate 0.006324 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dcache.occ_%::0 0.054908 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.occ_%::1 -0.015654 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.occ_blocks::0 28.113086 # Average occupied blocks per context
|
|
system.cpu3.dcache.occ_blocks::1 -8.014642 # Average occupied blocks per context
|
|
system.cpu3.dcache.overall_accesses 42223 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu3.dcache.overall_hits 41904 # number of overall hits
|
|
system.cpu3.dcache.overall_miss_latency 6082500 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_rate 0.007555 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_misses 319 # number of overall misses
|
|
system.cpu3.dcache.overall_mshr_hits 52 # number of overall MSHR hits
|
|
system.cpu3.dcache.overall_mshr_miss_latency 3927000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_rate 0.006324 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_misses 267 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu3.dcache.replacements 2 # number of replacements
|
|
system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu3.dcache.tagsinuse 20.098444 # Cycle average of tags in use
|
|
system.cpu3.dcache.total_refs 24305 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.writebacks 1 # number of writebacks
|
|
system.cpu3.decode.DECODE:BlockedCycles 35593 # Number of cycles decode is blocked
|
|
system.cpu3.decode.DECODE:DecodedInsts 394229 # Number of instructions handled by decode
|
|
system.cpu3.decode.DECODE:IdleCycles 164873 # Number of cycles decode is idle
|
|
system.cpu3.decode.DECODE:RunCycles 145919 # Number of cycles decode is running
|
|
system.cpu3.decode.DECODE:SquashCycles 36967 # Number of cycles decode is squashing
|
|
system.cpu3.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking
|
|
system.cpu3.fetch.Branches 82266 # Number of branches that fetch encountered
|
|
system.cpu3.fetch.CacheLines 80954 # Number of cache lines fetched
|
|
system.cpu3.fetch.Cycles 235714 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu3.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed
|
|
system.cpu3.fetch.Insts 435938 # Number of instructions fetch has processed
|
|
system.cpu3.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing
|
|
system.cpu3.fetch.branchRate 0.208424 # Number of branch fetches per cycle
|
|
system.cpu3.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu3.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken
|
|
system.cpu3.fetch.rate 1.104465 # Number of inst fetches per cycle
|
|
system.cpu3.fetch.rateDist::samples 392184 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::mean 1.111565 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::stdev 2.082267 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::0 237449 60.55% 60.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::1 82939 21.15% 81.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::2 12394 3.16% 84.85% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::3 15941 4.06% 88.92% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::4 2706 0.69% 89.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::5 16830 4.29% 93.90% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::6 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::7 2412 0.62% 94.97% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::8 19726 5.03% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::total 392184 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_hits 80218 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_miss_latency 10255000 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_rate 0.009092 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_misses 736 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency 7339500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate 0.007893 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_misses 639 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_refs 125.536776 # Average number of references to valid blocks.
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.demand_accesses 80954 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_avg_miss_latency 13933.423913 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_hits 80218 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_miss_latency 10255000 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_rate 0.009092 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_misses 736 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.demand_mshr_miss_latency 7339500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_rate 0.007893 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_misses 639 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.icache.occ_%::0 0.189077 # Average percentage of cache occupancy
|
|
system.cpu3.icache.occ_blocks::0 96.807549 # Average occupied blocks per context
|
|
system.cpu3.icache.overall_accesses 80954 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu3.icache.overall_hits 80218 # number of overall hits
|
|
system.cpu3.icache.overall_miss_latency 10255000 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_rate 0.009092 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_misses 736 # number of overall misses
|
|
system.cpu3.icache.overall_mshr_hits 97 # number of overall MSHR hits
|
|
system.cpu3.icache.overall_mshr_miss_latency 7339500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_rate 0.007893 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_misses 639 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu3.icache.replacements 527 # number of replacements
|
|
system.cpu3.icache.sampled_refs 639 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu3.icache.tagsinuse 96.807549 # Cycle average of tags in use
|
|
system.cpu3.icache.total_refs 80218 # Total number of references to valid blocks.
|
|
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.writebacks 0 # number of writebacks
|
|
system.cpu3.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu3.iew.EXEC:branches 39408 # Number of branches executed
|
|
system.cpu3.iew.EXEC:nop 47237 # number of nop insts executed
|
|
system.cpu3.iew.EXEC:rate 0.449837 # Inst execution rate
|
|
system.cpu3.iew.EXEC:refs 53769 # number of memory reference insts executed
|
|
system.cpu3.iew.EXEC:stores 15425 # Number of stores executed
|
|
system.cpu3.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu3.iew.WB:consumers 88234 # num instructions consuming a value
|
|
system.cpu3.iew.WB:count 173934 # cumulative count of insts written-back
|
|
system.cpu3.iew.WB:fanout 0.937246 # average fanout of values written-back
|
|
system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu3.iew.WB:producers 82697 # num instructions producing a value
|
|
system.cpu3.iew.WB:rate 0.440668 # insts written-back per cycle
|
|
system.cpu3.iew.WB:sent 174194 # cumulative count of insts sent to commit
|
|
system.cpu3.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute
|
|
system.cpu3.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
|
system.cpu3.iew.iewDispLoadInsts 43341 # Number of dispatched load instructions
|
|
system.cpu3.iew.iewDispNonSpecInsts 11749 # Number of dispatched non-speculative instructions
|
|
system.cpu3.iew.iewDispSquashedInsts 3545 # Number of squashed instructions skipped by dispatch
|
|
system.cpu3.iew.iewDispStoreInsts 27172 # Number of dispatched store instructions
|
|
system.cpu3.iew.iewDispatchedInsts 284714 # Number of instructions dispatched to IQ
|
|
system.cpu3.iew.iewExecLoadInsts 38344 # Number of load instructions executed
|
|
system.cpu3.iew.iewExecSquashedInsts 36975 # Number of squashed instructions skipped in execute
|
|
system.cpu3.iew.iewExecutedInsts 177553 # Number of executed instructions
|
|
system.cpu3.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu3.iew.iewSquashCycles 36967 # Number of cycles IEW is squashing
|
|
system.cpu3.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu3.iew.lsq.thread.0.forwLoads 9839 # Number of loads that had data forwarded from stores
|
|
system.cpu3.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread.0.memOrderViolation 701 # Number of memory ordering violations
|
|
system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu3.iew.lsq.thread.0.squashedLoads 10926 # Number of loads squashed
|
|
system.cpu3.iew.lsq.thread.0.squashedStores 13369 # Number of stores squashed
|
|
system.cpu3.iew.memOrderViolationEvents 701 # Number of memory order violations
|
|
system.cpu3.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu3.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly
|
|
system.cpu3.ipc 0.281547 # IPC: Instructions Per Cycle
|
|
system.cpu3.ipc_total 0.281547 # IPC: Total IPC of All Threads
|
|
system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.57% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.57% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.57% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.57% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.57% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.57% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.57% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::MemRead 44868 20.91% 92.48% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::MemWrite 16122 7.52% 100.00% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::total 214528 # Type of FU issued
|
|
system.cpu3.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested
|
|
system.cpu3.iq.ISSUE:fu_busy_rate 0.000867 # FU busy rate (busy events/executed inst)
|
|
system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::samples 392184 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.547009 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.999225 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::0 270484 68.97% 68.97% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::1 66150 16.87% 85.84% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::2 30383 7.75% 93.58% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::3 16859 4.30% 97.88% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::4 5420 1.38% 99.26% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::5 2202 0.56% 99.83% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::6 491 0.13% 99.95% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::total 392184 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:rate 0.543515 # Inst issue rate
|
|
system.cpu3.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu3.iq.iqInstsIssued 214528 # Number of instructions issued
|
|
system.cpu3.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ
|
|
system.cpu3.iq.iqSquashedInstsExamined 86635 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
|
|
system.cpu3.iq.iqSquashedNonSpecRemoved 11566 # Number of squashed non-spec instructions that were removed
|
|
system.cpu3.iq.iqSquashedOperandsExamined 36678 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu3.memDep0.conflictingLoads 10938 # Number of conflicting loads.
|
|
system.cpu3.memDep0.conflictingStores 96 # Number of conflicting stores.
|
|
system.cpu3.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu3.numCycles 394705 # number of cpu cycles simulated
|
|
system.cpu3.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed
|
|
system.cpu3.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle
|
|
system.cpu3.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
|
system.cpu3.rename.RENAME:RenameLookups 494732 # Number of register rename lookups that rename has made
|
|
system.cpu3.rename.RENAME:RenamedInsts 312015 # Number of instructions processed by rename
|
|
system.cpu3.rename.RENAME:RenamedOperands 231166 # Number of destination operands rename has renamed
|
|
system.cpu3.rename.RENAME:RunCycles 130989 # Number of cycles rename is running
|
|
system.cpu3.rename.RENAME:SquashCycles 36967 # Number of cycles rename is squashing
|
|
system.cpu3.rename.RENAME:UnblockCycles 619 # Number of cycles rename is unblocking
|
|
system.cpu3.rename.RENAME:UndoneMaps 136540 # Number of HB maps that are undone due to squashing
|
|
system.cpu3.rename.RENAME:serializeStallCycles 34885 # count of cycles rename stalled for serializing inst
|
|
system.cpu3.rename.RENAME:serializingInsts 11999 # count of serializing insts renamed
|
|
system.cpu3.rename.RENAME:skidInsts 46061 # count of insts added to the skid buffer
|
|
system.cpu3.rename.RENAME:tempSerializingInsts 12120 # count of temporary serializing insts renamed
|
|
system.cpu3.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency::0 73117.021277 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::1 572750 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::2 528692.307692 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::3 572750 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 1747309.328969 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40309.160305 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_miss_latency 6873000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 5280500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses::0 751 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::1 650 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::2 646 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::3 653 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2700 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency::0 63452.850877 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::1 2225730.769231 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::2 361681.250000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::3 4822416.666667 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 7473281.536775 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 39996.370236 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_hits::0 295 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::1 637 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::2 566 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::3 647 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 2145 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 28934500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate::0 0.607190 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::1 0.020000 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::2 0.123839 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::3 0.009188 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.760218 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses::0 456 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::1 13 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::2 80 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::3 6 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 555 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_miss_latency 22038000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.733688 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::1 0.847692 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::2 0.852941 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::3 0.843798 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 3.278120 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 551 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_accesses::0 31 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::1 21 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::2 21 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::3 22 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 95 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 5625 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 7500 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::2 7500 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::3 7159.090909 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 27784.090909 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_miss_latency 157500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate::0 0.903226 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 3.903226 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses::0 28 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::1 21 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::2 21 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::3 22 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 92 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 3680000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 2.967742 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 4.380952 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::2 4.380952 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::3 4.181818 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 15.911465 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 92 # number of UpgradeReq MSHR misses
|
|
system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits::0 9 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 9 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 3.873418 # Average number of references to valid blocks.
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses::0 845 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::1 662 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::2 659 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::3 665 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2831 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency::0 65104.545455 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::1 1432300 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::2 385026.881720 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::3 1989305.555556 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 3871736.982731 # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40056.451613 # average overall mshr miss latency
|
|
system.l2c.demand_hits::0 295 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::1 637 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::2 566 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::3 647 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2145 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 35807500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate::0 0.650888 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::1 0.037764 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::2 0.141123 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::3 0.027068 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.856843 # miss rate for demand accesses
|
|
system.l2c.demand_misses::0 550 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::1 25 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::2 93 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::3 18 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 686 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 4 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 27318500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate::0 0.807101 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::1 1.030211 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::2 1.034901 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::3 1.025564 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 3.897777 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 682 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.occ_%::0 0.005838 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::1 0.000152 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::2 0.001069 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::3 0.000056 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::4 0.000091 # Average percentage of cache occupancy
|
|
system.l2c.occ_blocks::0 382.596816 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::1 9.957586 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::2 70.028959 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::3 3.647267 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::4 5.949685 # Average occupied blocks per context
|
|
system.l2c.overall_accesses::0 845 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::1 662 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::2 659 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::3 665 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2831 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency::0 65104.545455 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::1 1432300 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::2 385026.881720 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::3 1989305.555556 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 3871736.982731 # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40056.451613 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits::0 295 # number of overall hits
|
|
system.l2c.overall_hits::1 637 # number of overall hits
|
|
system.l2c.overall_hits::2 566 # number of overall hits
|
|
system.l2c.overall_hits::3 647 # number of overall hits
|
|
system.l2c.overall_hits::total 2145 # number of overall hits
|
|
system.l2c.overall_miss_latency 35807500 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate::0 0.650888 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::1 0.037764 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::2 0.141123 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::3 0.027068 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.856843 # miss rate for overall accesses
|
|
system.l2c.overall_misses::0 550 # number of overall misses
|
|
system.l2c.overall_misses::1 25 # number of overall misses
|
|
system.l2c.overall_misses::2 93 # number of overall misses
|
|
system.l2c.overall_misses::3 18 # number of overall misses
|
|
system.l2c.overall_misses::total 686 # number of overall misses
|
|
system.l2c.overall_mshr_hits 4 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 27318500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate::0 0.807101 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::1 1.030211 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::2 1.034901 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::3 1.025564 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 3.897777 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 682 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 0 # number of replacements
|
|
system.l2c.sampled_refs 553 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 472.180314 # Cycle average of tags in use
|
|
system.l2c.total_refs 2142 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 0 # number of writebacks
|
|
|
|
---------- End Simulation Statistics ----------
|