9e45ada171
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
19 lines
1,004 B
Text
Executable file
19 lines
1,004 B
Text
Executable file
Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
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Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
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M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Aug 26 2010 12:51:14
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M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
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M5 started Aug 26 2010 12:51:16
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M5 executing on zizzer
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command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/m5/system/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 1927951878000 because m5_exit instruction encountered
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