gem5/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
Steve Reinhardt 9e45ada171 stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00

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Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:58:58
M5 executing on zizzer
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
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122 123 124 Exiting @ tick 118742021000 because target called exit()