9e45ada171
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
33 lines
1.7 KiB
Text
Executable file
33 lines
1.7 KiB
Text
Executable file
Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simout
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Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simerr
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M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Aug 26 2010 11:51:59
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M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
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M5 started Aug 26 2010 11:58:58
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M5 executing on zizzer
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command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
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Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
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Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
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Standard Cell Placement and Global Routing Program
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Authors: Carl Sechen, Bill Swartz
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Yale University
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91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
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106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
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122 123 124 Exiting @ tick 118742021000 because target called exit()
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