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gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
Steve Reinhardt 9e45ada171 stats: update stats for preceding coherence changes 
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00

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---------- Begin Simulation Statistics ----------
host_inst_rate 1235575 # Simulator instruction rate (inst/s)
host_mem_usage 206704 # Number of bytes of host memory used
host_seconds 1472.82 # Real time elapsed on the host
host_tick_rate 1836801554 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.705279 # Number of seconds simulated
sim_ticks 2705279137000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24619.494258 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21619.494258 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 177812180000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 156144938000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 52453.824926 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49453.824926 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 158727823 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 104943266000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.012448 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2000679 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 98941229000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.012448 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2000679 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30657.334367 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency
system.cpu.dcache.demand_hits 596101072 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 282755446000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.015237 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9223093 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 255086167000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.015237 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9223093 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.996035 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4079.758997 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30657.334367 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 596101072 # number of overall hits
system.cpu.dcache.overall_miss_latency 282755446000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.015237 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9223093 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 255086167000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.015237 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9223093 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4079.758997 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 40990273000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2365949 # number of writebacks
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.298761 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 611.862910 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1826377708 # number of overall hits
system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_misses 802 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 611.862910 # Cycle average of tags in use
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 1826378510 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 168921 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 89460748000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.910592 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1720399 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68815960000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.910592 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1720399 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5396262 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 95001608000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.252928 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1826954 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 73078160000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252928 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1826954 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 111359 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51964.511176 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 5786716000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 111359 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4454360000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 111359 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2365949 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2365949 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.515193 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5565183 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 184462356000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.389283 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3547353 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 141894120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.389283 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 3547353 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.466649 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.320836 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15291.153152 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10513.160578 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5565183 # number of overall hits
system.cpu.l2cache.overall_miss_latency 184462356000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.389283 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3547353 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 141894120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.389283 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 3547353 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 2701645 # number of replacements
system.cpu.l2cache.sampled_refs 2726277 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 25804.313731 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6857112 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 596452524000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1175830 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5410558274 # number of cpu cycles simulated
system.cpu.num_insts 1819780127 # Number of instructions executed
system.cpu.num_refs 613169725 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
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