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gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
Steve Reinhardt 9e45ada171 stats: update stats for preceding coherence changes 
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00

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---------- Begin Simulation Statistics ----------
host_inst_rate 83534 # Simulator instruction rate (inst/s)
host_mem_usage 292436 # Number of bytes of host memory used
host_seconds 635.06 # Real time elapsed on the host
host_tick_rate 2937207030 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 53048754 # Number of instructions simulated
sim_seconds 1.865288 # Number of seconds simulated
sim_ticks 1865288389500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 6766434 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 12986969 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 41472 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 813466 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 12097848 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 14524578 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1028567 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 8457223 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 1009026 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 98617953 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.570296 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.335991 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 74454640 75.50% 75.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 10711227 10.86% 86.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 5970777 6.05% 92.41% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 2911969 2.95% 95.37% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2119464 2.15% 97.52% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 692478 0.70% 98.22% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 398357 0.40% 98.62% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 350015 0.35% 98.98% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 1009026 1.02% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 98617953 # Number of insts commited each cycle
system.cpu.commit.COM:count 56241389 # Number of instructions committed
system.cpu.commit.COM:loads 9301917 # Number of loads committed
system.cpu.commit.COM:membars 227986 # Number of memory barriers committed
system.cpu.commit.COM:refs 15690474 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 771977 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 56241389 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 667741 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 9346936 # The number of squashed insts skipped by commit
system.cpu.committedInsts 53048754 # Number of Instructions Simulated
system.cpu.committedInsts_total 53048754 # Number of Instructions Simulated
system.cpu.cpi 2.541919 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.541919 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses::0 214829 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 214829 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15450.383219 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11789.484229 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits::0 192518 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 192518 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 344713500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103855 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0 22311 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22311 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 4842 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205950500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081316 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 17469 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses::0 9301988 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9301988 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::0 23801.813261 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22758.438856 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_hits::0 7781909 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7781909 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 36180636500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate::0 0.163414 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::0 1520079 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1520079 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 436579 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 24658768500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116480 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1083500 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904975000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses::0 219792 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 219792 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56335.990566 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53335.990566 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_hits::0 198592 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 198592 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_latency 1194323000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_rate::0 0.096455 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses::0 21200 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 21200 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_latency 1130723000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.096455 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses 21200 # number of StoreCondReq MSHR misses
system.cpu.dcache.WriteReq_accesses::0 6153614 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6153614 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency::0 48733.687858 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53794.875061 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_hits::0 3986142 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 3986142 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 105628903889 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate::0 0.352227 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::0 2167472 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2167472 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1799517 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 19794093253 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.059795 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 367955 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235122997 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9816.976394 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 17750 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 8.810921 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 136746 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 1342432254 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 35500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses::0 15455602 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15455602 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0 38456.292642 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 30626.414014 # average overall mshr miss latency
system.cpu.dcache.demand_hits::0 11768051 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 11768051 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 141809540389 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::0 0.238590 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.dcache.demand_misses::0 3687551 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3687551 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2236096 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 44452861753 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0.093911 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1451455 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy
system.cpu.dcache.occ_%::1 -0.007635 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 511.995459 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::1 -3.909039 # Average occupied blocks per context
system.cpu.dcache.overall_accesses::0 15455602 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15455602 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::0 38456.292642 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 30626.414014 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits::0 11768051 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
system.cpu.dcache.overall_hits::total 11768051 # number of overall hits
system.cpu.dcache.overall_miss_latency 141809540389 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::0 0.238590 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.dcache.overall_misses::0 3687551 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
system.cpu.dcache.overall_misses::total 3687551 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2236096 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 44452861753 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0.093911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1451455 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 2140097997 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1400442 # number of replacements
system.cpu.dcache.sampled_refs 1400954 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 510.040943 # Cycle average of tags in use
system.cpu.dcache.total_refs 12343695 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 455265 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 46660710 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 42482 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 616847 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 72473028 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 37849528 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 12958836 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1616629 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 135444 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1148878 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 1239402 # DTB accesses
system.cpu.dtb.data_acv 830 # DTB access violations
system.cpu.dtb.data_hits 16737953 # DTB hits
system.cpu.dtb.data_misses 44771 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 913549 # DTB read accesses
system.cpu.dtb.read_acv 594 # DTB read access violations
system.cpu.dtb.read_hits 10142643 # DTB read hits
system.cpu.dtb.read_misses 36670 # DTB read misses
system.cpu.dtb.write_accesses 325853 # DTB write accesses
system.cpu.dtb.write_acv 236 # DTB write access violations
system.cpu.dtb.write_hits 6595310 # DTB write hits
system.cpu.dtb.write_misses 8101 # DTB write misses
system.cpu.fetch.Branches 14524578 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 8948260 # Number of cache lines fetched
system.cpu.fetch.Cycles 23311047 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 456775 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 73989590 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 2537 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 952530 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.107713 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 8948260 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 7795001 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.548698 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 100234582 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.738164 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.038365 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 85912196 85.71% 85.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1042441 1.04% 86.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1978378 1.97% 88.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 936363 0.93% 89.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2989129 2.98% 92.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 664727 0.66% 93.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 787515 0.79% 94.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1214601 1.21% 95.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 4709232 4.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 100234582 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses::0 8948260 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 8948260 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::0 14907.888251 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11902.318660 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits::0 7903415 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7903415 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 15576432500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate::0 0.116765 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::0 1044845 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1044845 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 50305 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 11837332000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111143 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 994540 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs 12104.838710 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 7.948315 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 62 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 750500 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses::0 8948260 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 8948260 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::0 14907.888251 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11902.318660 # average overall mshr miss latency
system.cpu.icache.demand_hits::0 7903415 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7903415 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 15576432500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::0 0.116765 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.icache.demand_misses::0 1044845 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1044845 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 50305 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 11837332000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::0 0.111143 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 994540 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.995598 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 509.746088 # Average occupied blocks per context
system.cpu.icache.overall_accesses::0 8948260 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 8948260 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::0 14907.888251 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11902.318660 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits::0 7903415 # number of overall hits
system.cpu.icache.overall_hits::1 0 # number of overall hits
system.cpu.icache.overall_hits::total 7903415 # number of overall hits
system.cpu.icache.overall_miss_latency 15576432500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate::0 0.116765 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.icache.overall_misses::0 1044845 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
system.cpu.icache.overall_misses::total 1044845 # number of overall misses
system.cpu.icache.overall_mshr_hits 50305 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 11837332000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::0 0.111143 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 994540 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 993840 # number of replacements
system.cpu.icache.sampled_refs 994351 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 509.746088 # Cycle average of tags in use
system.cpu.icache.total_refs 7903415 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 25251004000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 5 # number of writebacks
system.cpu.idleCycles 34611048 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 9149461 # Number of branches executed
system.cpu.iew.EXEC:nop 3645494 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.426187 # Inst execution rate
system.cpu.iew.EXEC:refs 17021543 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 6618330 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 34491432 # num instructions consuming a value
system.cpu.iew.WB:count 56873596 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.763558 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 26336207 # num instructions producing a value
system.cpu.iew.WB:rate 0.421768 # insts written-back per cycle
system.cpu.iew.WB:sent 56969504 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 835772 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 9640204 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 11032857 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1798988 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1002562 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 7014115 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 65718389 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 10403213 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 554442 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 57469408 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 44506 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 6661 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1616629 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 544895 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 306779 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 434666 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 11993 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 45591 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 18153 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1730940 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 625558 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 45591 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 404736 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 431036 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.393404 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.393404 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7283 0.01% 0.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 39532589 68.13% 68.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 62065 0.11% 68.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25614 0.04% 68.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 10774153 18.57% 86.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 6665338 11.49% 98.36% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 953173 1.64% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 58023852 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 434401 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.007487 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 47887 11.02% 11.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 281518 64.81% 75.83% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 104996 24.17% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 100234582 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.578881 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.146223 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 71270288 71.10% 71.10% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 14553068 14.52% 85.62% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 6335877 6.32% 91.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 3893576 3.88% 95.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 2543708 2.54% 98.37% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 1056426 1.05% 99.42% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 441326 0.44% 99.86% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 109120 0.11% 99.97% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 31193 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 100234582 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.430298 # Inst issue rate
system.cpu.iq.iqInstsAdded 60022452 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 58023852 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 2050443 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 8631662 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 41705 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 1382702 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 4647656 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 1304111 # ITB accesses
system.cpu.itb.fetch_acv 934 # ITB acv
system.cpu.itb.fetch_hits 1264639 # ITB hits
system.cpu.itb.fetch_misses 39472 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl 175665 91.19% 93.39% # number of callpals executed
system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
system.cpu.kern.callpal::rti 5219 2.71% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 192634 # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.hwrei 211790 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed
system.cpu.kern.ipl_count::0 74955 40.96% 40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 237 0.13% 41.09% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1888 1.03% 42.12% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105930 57.88% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 183010 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73588 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1888 1.26% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73588 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149301 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1823061244500 97.74% 97.74% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 98162000 0.01% 97.74% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 391950000 0.02% 97.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 41736158500 2.24% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1865287515000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981762 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.694685 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good::kernel 1909
system.cpu.kern.mode_good::user 1739
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch::kernel 5970 # number of protection mode switches
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
system.cpu.kern.mode_switch_good::kernel 0.319765 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 1.400911 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 31031458000 1.66% 1.66% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 3177312000 0.17% 1.83% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1831078737000 98.17% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4179 # number of times the context was actually changed
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.memDep0.conflictingLoads 3098880 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2694658 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 11032857 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 7014115 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 134845630 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 14093810 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 38225332 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1080811 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 39441227 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2214917 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 14670 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 83145881 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 68419430 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 45844130 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 12603060 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1616629 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 5180630 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 7618796 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 27299224 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 1703562 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 12710348 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 255623 # count of temporary serializing insts renamed
system.cpu.timesIdled 1320206 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137804.625674 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85801.092270 # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency 5726057806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency 3565206986 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles::no_mshrs 6169.984712 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs 10466 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs 64575060 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137711.103751 # average overall miss latency
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 85707.584997 # average overall mshr miss latency
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 5745995804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 3576148984 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.occ_%::1 0.078725 # Average percentage of cache occupancy
system.iocache.occ_blocks::1 1.259600 # Average occupied blocks per context
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137711.103751 # average overall miss latency
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 85707.584997 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
system.iocache.overall_miss_latency 5745995804 # number of overall miss cycles
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::0 0 # number of overall misses
system.iocache.overall_misses::1 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 3576148984 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.replacements 41685 # number of replacements
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse 1.259600 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1715198512000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
system.l2c.ReadExReq_accesses::0 300711 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 300711 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 52369.611662 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40214.373242 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_hits::0 2213 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 2213 # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency 15632224342 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 0.992641 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 298498 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 298498 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 12003909984 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 0.992641 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 298498 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0 2094821 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2094821 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0 52048.515602 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40015.565251 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits::0 1784931 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1784931 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 16129314500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.147931 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 309890 # number of ReadReq misses
system.l2c.ReadReq_misses::total 309890 # number of ReadReq misses
system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency 12400383500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.147931 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 309889 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 810515000 # number of ReadReq MSHR uncacheable cycles
system.l2c.SCUpgradeReq_accesses::0 21199 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 21199 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_avg_miss_latency::0 52327.059157 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000.731201 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_hits::0 1 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_miss_latency 1109229000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_rate::0 0.999953 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_misses::0 21198 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 21198 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_mshr_miss_latency 847935500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.999953 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_misses 21198 # number of SCUpgradeReq MSHR misses
system.l2c.UpgradeReq_accesses::0 69854 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 69854 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0 52150.764423 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40013.263378 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 3642939498 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0 69854 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 69854 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 2795086500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 69854 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 1115590498 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0 455270 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 455270 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 455270 # number of Writeback hits
system.l2c.Writeback_hits::total 455270 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 4.693284 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses::0 2395532 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2395532 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 52206.057388 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40113.108078 # average overall mshr miss latency
system.l2c.demand_hits::0 1787144 # number of demand (read+write) hits
system.l2c.demand_hits::1 0 # number of demand (read+write) hits
system.l2c.demand_hits::total 1787144 # number of demand (read+write) hits
system.l2c.demand_miss_latency 31761538842 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.253968 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
system.l2c.demand_misses::0 608388 # number of demand (read+write) misses
system.l2c.demand_misses::1 0 # number of demand (read+write) misses
system.l2c.demand_misses::total 608388 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 24404293484 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0.253967 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 608387 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_%::0 0.176515 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.325488 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 11568.063937 # Average occupied blocks per context
system.l2c.occ_blocks::1 21331.159568 # Average occupied blocks per context
system.l2c.overall_accesses::0 2395532 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2395532 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 52206.057388 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40113.108078 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.overall_hits::0 1787144 # number of overall hits
system.l2c.overall_hits::1 0 # number of overall hits
system.l2c.overall_hits::total 1787144 # number of overall hits
system.l2c.overall_miss_latency 31761538842 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.253968 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
system.l2c.overall_misses::0 608388 # number of overall misses
system.l2c.overall_misses::1 0 # number of overall misses
system.l2c.overall_misses::total 608388 # number of overall misses
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 24404293484 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0.253967 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 608387 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 1926105498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 394069 # number of replacements
system.l2c.sampled_refs 426267 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 32899.223505 # Cycle average of tags in use
system.l2c.total_refs 2000592 # Total number of references to valid blocks.
system.l2c.warmup_cycle 5644310000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 118209 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
---------- End Simulation Statistics ----------
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