c0ab52799c
When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it.
397 lines
15 KiB
C++
397 lines
15 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#ifndef __CPU_STATIC_INST_HH__
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#define __CPU_STATIC_INST_HH__
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#include <bitset>
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#include <string>
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#include "arch/registers.hh"
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#include "arch/types.hh"
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#include "base/misc.hh"
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#include "base/refcnt.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/op_class.hh"
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#include "cpu/static_inst_fwd.hh"
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#include "cpu/thread_context.hh"
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#include "sim/fault_fwd.hh"
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// forward declarations
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struct AlphaSimpleImpl;
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struct OzoneImpl;
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struct SimpleImpl;
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class DynInst;
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class Packet;
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struct O3CPUImpl;
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template <class Impl> class BaseO3DynInst;
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typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
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template <class Impl> class OzoneDynInst;
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class InOrderDynInst;
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class CheckerCPU;
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class FastCPU;
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class AtomicSimpleCPU;
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class TimingSimpleCPU;
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class InorderCPU;
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class SymbolTable;
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namespace Trace {
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class InstRecord;
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}
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/**
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* Base, ISA-independent static instruction class.
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*
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* The main component of this class is the vector of flags and the
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* associated methods for reading them. Any object that can rely
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* solely on these flags can process instructions without being
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* recompiled for multiple ISAs.
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*/
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class StaticInst : public RefCounted
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{
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public:
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/// Binary extended machine instruction type.
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typedef TheISA::ExtMachInst ExtMachInst;
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/// Logical register index type.
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typedef TheISA::RegIndex RegIndex;
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enum {
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MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
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MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
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};
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/// Set of boolean static instruction properties.
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///
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/// Notes:
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/// - The IsInteger and IsFloating flags are based on the class of
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/// registers accessed by the instruction. Although most
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/// instructions will have exactly one of these two flags set, it
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/// is possible for an instruction to have neither (e.g., direct
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/// unconditional branches, memory barriers) or both (e.g., an
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/// FP/int conversion).
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/// - If IsMemRef is set, then exactly one of IsLoad or IsStore
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/// will be set.
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/// - If IsControl is set, then exactly one of IsDirectControl or
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/// IsIndirect Control will be set, and exactly one of
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/// IsCondControl or IsUncondControl will be set.
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/// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
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/// implemented as flags since in the current model there's no
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/// other way for instructions to inject behavior into the
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/// pipeline outside of fetch. Once we go to an exec-in-exec CPU
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/// model we should be able to get rid of these flags and
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/// implement this behavior via the execute() methods.
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///
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enum Flags {
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IsNop, ///< Is a no-op (no effect at all).
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IsInteger, ///< References integer regs.
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IsFloating, ///< References FP regs.
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IsMemRef, ///< References memory (load, store, or prefetch).
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IsLoad, ///< Reads from memory (load or prefetch).
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IsStore, ///< Writes to memory.
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IsStoreConditional, ///< Store conditional instruction.
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IsIndexed, ///< Accesses memory with an indexed address computation
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IsInstPrefetch, ///< Instruction-cache prefetch.
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IsDataPrefetch, ///< Data-cache prefetch.
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IsControl, ///< Control transfer instruction.
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IsDirectControl, ///< PC relative control transfer.
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IsIndirectControl, ///< Register indirect control transfer.
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IsCondControl, ///< Conditional control transfer.
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IsUncondControl, ///< Unconditional control transfer.
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IsCall, ///< Subroutine call.
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IsReturn, ///< Subroutine return.
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IsCondDelaySlot,///< Conditional Delay-Slot Instruction
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IsThreadSync, ///< Thread synchronization operation.
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IsSerializing, ///< Serializes pipeline: won't execute until all
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/// older instructions have committed.
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IsSerializeBefore,
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IsSerializeAfter,
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IsMemBarrier, ///< Is a memory barrier
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IsWriteBarrier, ///< Is a write barrier
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IsReadBarrier, ///< Is a read barrier
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IsERET, /// <- Causes the IFU to stall (MIPS ISA)
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IsNonSpeculative, ///< Should not be executed speculatively
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IsQuiesce, ///< Is a quiesce instruction
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IsIprAccess, ///< Accesses IPRs
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IsUnverifiable, ///< Can't be verified by a checker
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IsSyscall, ///< Causes a system call to be emulated in syscall
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/// emulation mode.
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//Flags for microcode
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IsMacroop, ///< Is a macroop containing microops
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IsMicroop, ///< Is a microop
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IsDelayedCommit, ///< This microop doesn't commit right away
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IsLastMicroop, ///< This microop ends a microop sequence
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IsFirstMicroop, ///< This microop begins a microop sequence
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//This flag doesn't do anything yet
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IsMicroBranch, ///< This microop branches within the microcode for a macroop
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IsDspOp,
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IsSquashAfter, ///< Squash all uncommitted state after executed
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NumFlags
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};
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protected:
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/// Flag values for this instruction.
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std::bitset<NumFlags> flags;
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/// See opClass().
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OpClass _opClass;
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/// See numSrcRegs().
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int8_t _numSrcRegs;
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/// See numDestRegs().
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int8_t _numDestRegs;
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/// The following are used to track physical register usage
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/// for machines with separate int & FP reg files.
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//@{
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int8_t _numFPDestRegs;
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int8_t _numIntDestRegs;
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//@}
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public:
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/// @name Register information.
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/// The sum of numFPDestRegs() and numIntDestRegs() equals
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/// numDestRegs(). The former two functions are used to track
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/// physical register usage for machines with separate int & FP
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/// reg files.
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//@{
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/// Number of source registers.
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int8_t numSrcRegs() const { return _numSrcRegs; }
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/// Number of destination registers.
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int8_t numDestRegs() const { return _numDestRegs; }
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/// Number of floating-point destination regs.
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int8_t numFPDestRegs() const { return _numFPDestRegs; }
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/// Number of integer destination regs.
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int8_t numIntDestRegs() const { return _numIntDestRegs; }
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//@}
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/// @name Flag accessors.
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/// These functions are used to access the values of the various
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/// instruction property flags. See StaticInst::Flags for descriptions
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/// of the individual flags.
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//@{
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bool isNop() const { return flags[IsNop]; }
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bool isMemRef() const { return flags[IsMemRef]; }
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bool isLoad() const { return flags[IsLoad]; }
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bool isStore() const { return flags[IsStore]; }
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bool isStoreConditional() const { return flags[IsStoreConditional]; }
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bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
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bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
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bool isPrefetch() const { return isInstPrefetch() ||
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isDataPrefetch(); }
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bool isInteger() const { return flags[IsInteger]; }
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bool isFloating() const { return flags[IsFloating]; }
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bool isControl() const { return flags[IsControl]; }
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bool isCall() const { return flags[IsCall]; }
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bool isReturn() const { return flags[IsReturn]; }
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bool isDirectCtrl() const { return flags[IsDirectControl]; }
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bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
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bool isCondCtrl() const { return flags[IsCondControl]; }
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bool isUncondCtrl() const { return flags[IsUncondControl]; }
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bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
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bool isThreadSync() const { return flags[IsThreadSync]; }
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bool isSerializing() const { return flags[IsSerializing] ||
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flags[IsSerializeBefore] ||
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flags[IsSerializeAfter]; }
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bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
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bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
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bool isSquashAfter() const { return flags[IsSquashAfter]; }
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bool isMemBarrier() const { return flags[IsMemBarrier]; }
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bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
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bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
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bool isQuiesce() const { return flags[IsQuiesce]; }
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bool isIprAccess() const { return flags[IsIprAccess]; }
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bool isUnverifiable() const { return flags[IsUnverifiable]; }
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bool isSyscall() const { return flags[IsSyscall]; }
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bool isMacroop() const { return flags[IsMacroop]; }
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bool isMicroop() const { return flags[IsMicroop]; }
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bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
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bool isLastMicroop() const { return flags[IsLastMicroop]; }
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bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
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//This flag doesn't do anything yet
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bool isMicroBranch() const { return flags[IsMicroBranch]; }
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//@}
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void setLastMicroop() { flags[IsLastMicroop] = true; }
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void setDelayedCommit() { flags[IsDelayedCommit] = true; }
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void setFlag(Flags f) { flags[f] = true; }
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/// Operation class. Used to select appropriate function unit in issue.
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OpClass opClass() const { return _opClass; }
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/// Return logical index (architectural reg num) of i'th destination reg.
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/// Only the entries from 0 through numDestRegs()-1 are valid.
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RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
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/// Return logical index (architectural reg num) of i'th source reg.
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/// Only the entries from 0 through numSrcRegs()-1 are valid.
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RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
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/// Pointer to a statically allocated "null" instruction object.
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/// Used to give eaCompInst() and memAccInst() something to return
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/// when called on non-memory instructions.
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static StaticInstPtr nullStaticInstPtr;
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/**
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* Memory references only: returns "fake" instruction representing
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* the effective address part of the memory operation. Used to
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* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
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* just the EA computation.
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*/
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virtual const
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StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
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/**
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* Memory references only: returns "fake" instruction representing
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* the memory access part of the memory operation. Used to
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* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
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* just the memory access (not the EA computation).
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*/
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virtual const
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StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
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/// The binary machine instruction.
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const ExtMachInst machInst;
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protected:
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/// See destRegIdx().
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RegIndex _destRegIdx[MaxInstDestRegs];
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/// See srcRegIdx().
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RegIndex _srcRegIdx[MaxInstSrcRegs];
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/**
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* Base mnemonic (e.g., "add"). Used by generateDisassembly()
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* methods. Also useful to readily identify instructions from
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* within the debugger when #cachedDisassembly has not been
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* initialized.
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*/
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const char *mnemonic;
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/**
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* String representation of disassembly (lazily evaluated via
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* disassemble()).
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*/
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mutable std::string *cachedDisassembly;
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/**
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* Internal function to generate disassembly string.
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*/
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virtual std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
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/// Constructor.
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/// It's important to initialize everything here to a sane
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/// default, since the decoder generally only overrides
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/// the fields that are meaningful for the particular
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/// instruction.
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StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
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: _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
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_numFPDestRegs(0), _numIntDestRegs(0),
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machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
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{ }
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public:
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virtual ~StaticInst();
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/**
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* The execute() signatures are auto-generated by scons based on the
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* set of CPU models we are compiling in today.
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*/
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#include "cpu/static_inst_exec_sigs.hh"
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virtual void advancePC(TheISA::PCState &pcState) const = 0;
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/**
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* Return the microop that goes with a particular micropc. This should
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* only be defined/used in macroops which will contain microops
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*/
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virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
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/**
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* Return the target address for a PC-relative branch.
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* Invalid if not a PC-relative branch (i.e. isDirectCtrl()
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* should be true).
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*/
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virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
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/**
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* Return the target address for an indirect branch (jump). The
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* register value is read from the supplied thread context, so
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* the result is valid only if the thread context is about to
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* execute the branch in question. Invalid if not an indirect
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* branch (i.e. isIndirectCtrl() should be true).
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*/
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virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
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/**
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* Return true if the instruction is a control transfer, and if so,
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* return the target address as well.
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*/
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bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
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TheISA::PCState &tgt) const;
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/**
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* Return string representation of disassembled instruction.
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* The default version of this function will call the internal
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* virtual generateDisassembly() function to get the string,
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* then cache it in #cachedDisassembly. If the disassembly
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* should not be cached, this function should be overridden directly.
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*/
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virtual const std::string &disassemble(Addr pc,
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const SymbolTable *symtab = 0) const;
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/// Return name of machine instruction
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std::string getName() { return mnemonic; }
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};
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#endif // __CPU_STATIC_INST_HH__
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