this will safeguard future code from trying to remove from the list twice. That code wouldnt break but would waste time.
307 lines
9.5 KiB
C++
307 lines
9.5 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include "arch/isa_traits.hh"
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#include "config/the_isa.hh"
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#include "cpu/inorder/cpu.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/reg_dep_map.hh"
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#include "debug/RegDepMap.hh"
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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RegDepMap::RegDepMap(int size)
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{
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regMap.resize(InOrderCPU::NumRegTypes);
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regMap[InOrderCPU::IntType].resize(NumIntRegs);
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regMap[InOrderCPU::FloatType].resize(NumFloatRegs);
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regMap[InOrderCPU::MiscType].resize(NumMiscRegs);
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}
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RegDepMap::~RegDepMap()
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{
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clear();
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}
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string
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RegDepMap::name()
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{
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return cpu->name() + ".RegDepMap";
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}
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std::string RegDepMap::mapNames[InOrderCPU::NumRegTypes] =
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{"IntReg", "FloatReg", "MiscReg"};
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void
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RegDepMap::setCPU(InOrderCPU *_cpu)
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{
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cpu = _cpu;
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}
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void
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RegDepMap::clear()
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{
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for (int i = 0; i < regMap.size(); i++) {
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for (int j = 0; j < regMap[j].size(); j++)
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regMap[i][j].clear();
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regMap[i].clear();
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}
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regMap.clear();
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}
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void
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RegDepMap::insert(DynInstPtr inst)
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{
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int dest_regs = inst->numDestRegs();
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DPRINTF(RegDepMap, "Setting Output Dependencies for [sn:%i] "
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", %s (dest. regs = %i).\n",
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inst->seqNum,
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inst->instName(),
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dest_regs);
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for (int i = 0; i < dest_regs; i++) {
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InOrderCPU::RegType reg_type;
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TheISA::RegIndex raw_idx = inst->destRegIdx(i);
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TheISA::RegIndex flat_idx = cpu->flattenRegIdx(raw_idx,
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reg_type,
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inst->threadNumber);
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DPRINTF(RegDepMap, "[sn:%i] #%i flattened %i to %i.\n",
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inst->seqNum, i, raw_idx, flat_idx);
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inst->flattenDestReg(i, flat_idx);
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if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
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DPRINTF(RegDepMap, "[sn:%i]: Ignoring Insert-Dependency tracking for "
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"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
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flat_idx);
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continue;
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}
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insert(reg_type, flat_idx, inst);
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}
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}
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void
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RegDepMap::insert(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
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{
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DPRINTF(RegDepMap, "Inserting [sn:%i] onto %s dep. list for "
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"reg. idx %i.\n", inst->seqNum, mapNames[reg_type],
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idx);
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regMap[reg_type][idx].push_back(inst);
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inst->setRegDepEntry();
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}
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void
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RegDepMap::remove(DynInstPtr inst)
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{
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if (inst->isRegDepEntry()) {
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int dest_regs = inst->numDestRegs();
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DPRINTF(RegDepMap, "Removing [sn:%i]'s entries from reg. dep. map. for "
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", %s (dest. regs = %i).\n",
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inst->seqNum,
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inst->instName(),
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dest_regs);
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for (int i = 0; i < dest_regs; i++) {
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RegIndex flat_idx = inst->flattenedDestRegIdx(i);
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InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
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// Merge Dyn Inst & CPU Result Types
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if (flat_idx == TheISA::ZeroReg &&
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reg_type == InOrderCPU::IntType) {
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DPRINTF(RegDepMap, "[sn:%i]: Ignoring Remove-Dependency tracking for "
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"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
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flat_idx);
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continue;
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}
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remove(reg_type, flat_idx, inst);
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}
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inst->clearRegDepEntry();
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}
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}
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void
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RegDepMap::remove(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
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{
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std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
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std::list<DynInstPtr>::iterator list_end = regMap[reg_type][idx].end();
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while (list_it != list_end) {
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if((*list_it) == inst) {
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DPRINTF(RegDepMap, "Removing [sn:%i] from %s dep. list for "
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"reg. idx %i.\n", inst->seqNum, mapNames[reg_type],
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idx);
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regMap[reg_type][idx].erase(list_it);
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return;
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}
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list_it++;
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}
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panic("[sn:%i] Did not find entry for %i, type:%i\n", inst->seqNum, idx, reg_type);
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}
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void
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RegDepMap::removeFront(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
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{
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std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
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DPRINTF(RegDepMap, "[tid:%u]: Removing dependency entry on reg. idx "
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"%i for [sn:%i].\n", inst->readTid(), idx, inst->seqNum);
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assert(list_it != regMap[reg_type][idx].end());
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assert(inst == (*list_it));
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regMap[reg_type][idx].erase(list_it);
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}
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bool
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RegDepMap::canRead(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
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{
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if (regMap[reg_type][idx].size() == 0)
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return true;
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std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
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if (inst->seqNum <= (*list_it)->seqNum) {
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return true;
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} else {
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DPRINTF(RegDepMap, "[sn:%i] Can't read from RegFile, [sn:%i] has "
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"not written it's value back yet.\n",
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inst->seqNum, (*list_it)->seqNum);
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return false;
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}
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}
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ThePipeline::DynInstPtr
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RegDepMap::canForward(uint8_t reg_type, unsigned reg_idx, DynInstPtr inst)
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{
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std::list<DynInstPtr>::iterator list_it = regMap[reg_type][reg_idx].begin();
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std::list<DynInstPtr>::iterator list_end = regMap[reg_type][reg_idx].end();
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DynInstPtr forward_inst = NULL;
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// Look for instruction immediately in front of requestor to supply
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// data
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while (list_it != list_end &&
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(*list_it)->seqNum < inst->seqNum) {
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forward_inst = (*list_it);
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list_it++;
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}
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if (forward_inst) {
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int dest_reg_idx = forward_inst->getDestIdxNum(reg_idx);
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assert(dest_reg_idx != -1);
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DPRINTF(RegDepMap, "[sn:%i] Found potential forwarding value for reg %i "
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" w/ [sn:%i] dest. reg. #%i\n",
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inst->seqNum, reg_idx, forward_inst->seqNum, dest_reg_idx);
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if (forward_inst->isExecuted() &&
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forward_inst->readResultTime(dest_reg_idx) < curTick()) {
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return forward_inst;
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} else {
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if (!forward_inst->isExecuted()) {
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DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
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"forwarding, [sn:%i] %s has not been executed yet.\n",
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inst->seqNum, forward_inst->seqNum, forward_inst->instName());
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} else if (forward_inst->readResultTime(dest_reg_idx) >= curTick()) {
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DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
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"forwarding, [sn:%i] executed on tick:%i.\n",
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inst->seqNum, forward_inst->seqNum,
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forward_inst->readResultTime(dest_reg_idx));
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}
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return NULL;
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}
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} else {
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DPRINTF(RegDepMap, "[sn:%i] No instruction found to forward from.\n",
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inst->seqNum);
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return NULL;
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}
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}
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bool
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RegDepMap::canWrite(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
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{
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if (regMap[reg_type][idx].size() == 0)
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return true;
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std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
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if (inst->seqNum <= (*list_it)->seqNum) {
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return true;
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} else {
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DPRINTF(RegDepMap, "[sn:%i] Can't write from RegFile: [sn:%i] "
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"has not written it's value back yet.\n", inst->seqNum,
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(*list_it)->seqNum);
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}
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return false;
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}
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void
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RegDepMap::dump()
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{
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for (int reg_type = 0; reg_type < InOrderCPU::NumRegTypes; reg_type++) {
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for (int idx=0; idx < regMap.size(); idx++) {
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if (regMap[idx].size() > 0) {
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cprintf("Reg #%i (size:%i): ", idx, regMap[reg_type][idx].size());
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std::list<DynInstPtr>::iterator list_it =
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regMap[reg_type][idx].begin();
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std::list<DynInstPtr>::iterator list_end =
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regMap[reg_type][idx].end();
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while (list_it != list_end) {
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cprintf("[sn:%i] ", (*list_it)->seqNum);
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list_it++;
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}
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cprintf("\n");
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}
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}
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}
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}
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