e8723310ef
Change-Id: If9ebb8488e8db587482ecfa99d2c12cfe5734fb9 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
630 lines
20 KiB
C++
630 lines
20 KiB
C++
/*
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* Copyright (c) 2012-2016 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Dave Greene
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* Steve Reinhardt
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* Ron Dreslinski
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* Andreas Hansson
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*/
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/**
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* @file
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* Describes a cache based on template policies.
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*/
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#ifndef __MEM_CACHE_CACHE_HH__
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#define __MEM_CACHE_CACHE_HH__
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#include <unordered_set>
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#include "base/misc.hh" // fatal, panic, and warn
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#include "enums/Clusivity.hh"
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#include "mem/cache/base.hh"
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#include "mem/cache/blk.hh"
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#include "mem/cache/mshr.hh"
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#include "mem/cache/tags/base.hh"
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#include "params/Cache.hh"
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#include "sim/eventq.hh"
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//Forward decleration
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class BasePrefetcher;
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/**
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* A template-policy based cache. The behavior of the cache can be altered by
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* supplying different template policies. TagStore handles all tag and data
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* storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
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*/
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class Cache : public BaseCache
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{
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protected:
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/**
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* The CPU-side port extends the base cache slave port with access
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* functions for functional, atomic and timing requests.
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*/
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class CpuSidePort : public CacheSlavePort
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{
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private:
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// a pointer to our specific cache implementation
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Cache *cache;
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protected:
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virtual bool recvTimingSnoopResp(PacketPtr pkt);
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virtual bool recvTimingReq(PacketPtr pkt);
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virtual Tick recvAtomic(PacketPtr pkt);
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virtual void recvFunctional(PacketPtr pkt);
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virtual AddrRangeList getAddrRanges() const;
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public:
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CpuSidePort(const std::string &_name, Cache *_cache,
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const std::string &_label);
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};
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/**
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* Override the default behaviour of sendDeferredPacket to enable
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* the memory-side cache port to also send requests based on the
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* current MSHR status. This queue has a pointer to our specific
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* cache implementation and is used by the MemSidePort.
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*/
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class CacheReqPacketQueue : public ReqPacketQueue
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{
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protected:
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Cache &cache;
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SnoopRespPacketQueue &snoopRespQueue;
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public:
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CacheReqPacketQueue(Cache &cache, MasterPort &port,
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SnoopRespPacketQueue &snoop_resp_queue,
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const std::string &label) :
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ReqPacketQueue(cache, port, label), cache(cache),
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snoopRespQueue(snoop_resp_queue) { }
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/**
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* Override the normal sendDeferredPacket and do not only
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* consider the transmit list (used for responses), but also
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* requests.
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*/
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virtual void sendDeferredPacket();
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/**
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* Check if there is a conflicting snoop response about to be
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* send out, and if so simply stall any requests, and schedule
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* a send event at the same time as the next snoop response is
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* being sent out.
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*/
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bool checkConflictingSnoop(Addr addr)
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{
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if (snoopRespQueue.hasAddr(addr)) {
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DPRINTF(CachePort, "Waiting for snoop response to be "
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"sent\n");
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Tick when = snoopRespQueue.deferredPacketReadyTime();
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schedSendEvent(when);
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return true;
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}
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return false;
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}
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};
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/**
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* The memory-side port extends the base cache master port with
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* access functions for functional, atomic and timing snoops.
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*/
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class MemSidePort : public CacheMasterPort
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{
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private:
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/** The cache-specific queue. */
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CacheReqPacketQueue _reqQueue;
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SnoopRespPacketQueue _snoopRespQueue;
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// a pointer to our specific cache implementation
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Cache *cache;
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protected:
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virtual void recvTimingSnoopReq(PacketPtr pkt);
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virtual bool recvTimingResp(PacketPtr pkt);
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virtual Tick recvAtomicSnoop(PacketPtr pkt);
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virtual void recvFunctionalSnoop(PacketPtr pkt);
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public:
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MemSidePort(const std::string &_name, Cache *_cache,
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const std::string &_label);
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};
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/** Tag and data Storage */
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BaseTags *tags;
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/** Prefetcher */
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BasePrefetcher *prefetcher;
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/** Temporary cache block for occasional transitory use */
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CacheBlk *tempBlock;
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/**
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* This cache should allocate a block on a line-sized write miss.
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*/
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const bool doFastWrites;
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/**
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* Turn line-sized writes into WriteInvalidate transactions.
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*/
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void promoteWholeLineWrites(PacketPtr pkt);
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/**
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* Notify the prefetcher on every access, not just misses.
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*/
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const bool prefetchOnAccess;
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/**
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* Clusivity with respect to the upstream cache, determining if we
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* fill into both this cache and the cache above on a miss. Note
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* that we currently do not support strict clusivity policies.
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*/
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const Enums::Clusivity clusivity;
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/**
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* Determine if clean lines should be written back or not. In
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* cases where a downstream cache is mostly inclusive we likely
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* want it to act as a victim cache also for lines that have not
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* been modified. Hence, we cannot simply drop the line (or send a
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* clean evict), but rather need to send the actual data.
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*/
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const bool writebackClean;
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/**
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* Upstream caches need this packet until true is returned, so
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* hold it for deletion until a subsequent call
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*/
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std::unique_ptr<Packet> pendingDelete;
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/**
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* Writebacks from the tempBlock, resulting on the response path
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* in atomic mode, must happen after the call to recvAtomic has
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* finished (for the right ordering of the packets). We therefore
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* need to hold on to the packets, and have a method and an event
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* to send them.
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*/
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PacketPtr tempBlockWriteback;
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/**
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* Send the outstanding tempBlock writeback. To be called after
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* recvAtomic finishes in cases where the block we filled is in
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* fact the tempBlock, and now needs to be written back.
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*/
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void writebackTempBlockAtomic() {
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assert(tempBlockWriteback != nullptr);
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PacketList writebacks{tempBlockWriteback};
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doWritebacksAtomic(writebacks);
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tempBlockWriteback = nullptr;
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}
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/**
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* An event to writeback the tempBlock after recvAtomic
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* finishes. To avoid other calls to recvAtomic getting in
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* between, we create this event with a higher priority.
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*/
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EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \
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writebackTempBlockAtomicEvent;
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/**
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* Store the outstanding requests that we are expecting snoop
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* responses from so we can determine which snoop responses we
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* generated and which ones were merely forwarded.
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*/
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std::unordered_set<RequestPtr> outstandingSnoop;
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/**
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* Does all the processing necessary to perform the provided request.
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* @param pkt The memory request to perform.
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* @param blk The cache block to be updated.
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* @param lat The latency of the access.
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* @param writebacks List for any writebacks that need to be performed.
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* @return Boolean indicating whether the request was satisfied.
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*/
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bool access(PacketPtr pkt, CacheBlk *&blk,
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Cycles &lat, PacketList &writebacks);
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/**
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*Handle doing the Compare and Swap function for SPARC.
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*/
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void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
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/**
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* Find a block frame for new block at address addr targeting the
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* given security space, assuming that the block is not currently
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* in the cache. Append writebacks if any to provided packet
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* list. Return free block frame. May return nullptr if there are
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* no replaceable blocks at the moment.
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*/
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CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
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/**
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* Invalidate a cache block.
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*
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* @param blk Block to invalidate
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*/
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void invalidateBlock(CacheBlk *blk);
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/**
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* Maintain the clusivity of this cache by potentially
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* invalidating a block. This method works in conjunction with
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* satisfyRequest, but is separate to allow us to handle all MSHR
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* targets before potentially dropping a block.
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*
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* @param from_cache Whether we have dealt with a packet from a cache
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* @param blk The block that should potentially be dropped
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*/
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void maintainClusivity(bool from_cache, CacheBlk *blk);
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/**
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* Populates a cache block and handles all outstanding requests for the
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* satisfied fill request. This version takes two memory requests. One
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* contains the fill data, the other is an optional target to satisfy.
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* @param pkt The memory request with the fill data.
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* @param blk The cache block if it already exists.
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* @param writebacks List for any writebacks that need to be performed.
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* @param allocate Whether to allocate a block or use the temp block
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* @return Pointer to the new cache block.
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*/
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CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
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PacketList &writebacks, bool allocate);
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/**
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* Determine whether we should allocate on a fill or not. If this
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* cache is mostly inclusive with regards to the upstream cache(s)
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* we always allocate (for any non-forwarded and cacheable
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* requests). In the case of a mostly exclusive cache, we allocate
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* on fill if the packet did not come from a cache, thus if we:
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* are dealing with a whole-line write (the latter behaves much
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* like a writeback), the original target packet came from a
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* non-caching source, or if we are performing a prefetch or LLSC.
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*
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* @param cmd Command of the incoming requesting packet
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* @return Whether we should allocate on the fill
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*/
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inline bool allocOnFill(MemCmd cmd) const override
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{
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return clusivity == Enums::mostly_incl ||
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cmd == MemCmd::WriteLineReq ||
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cmd == MemCmd::ReadReq ||
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cmd == MemCmd::WriteReq ||
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cmd.isPrefetch() ||
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cmd.isLLSC();
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}
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/**
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* Performs the access specified by the request.
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* @param pkt The request to perform.
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* @return The result of the access.
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*/
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bool recvTimingReq(PacketPtr pkt);
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/**
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* Insert writebacks into the write buffer
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*/
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void doWritebacks(PacketList& writebacks, Tick forward_time);
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/**
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* Send writebacks down the memory hierarchy in atomic mode
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*/
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void doWritebacksAtomic(PacketList& writebacks);
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/**
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* Handling the special case of uncacheable write responses to
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* make recvTimingResp less cluttered.
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*/
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void handleUncacheableWriteResp(PacketPtr pkt);
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/**
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* Handles a response (cache line fill/write ack) from the bus.
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* @param pkt The response packet
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*/
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void recvTimingResp(PacketPtr pkt);
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/**
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* Snoops bus transactions to maintain coherence.
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* @param pkt The current bus transaction.
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*/
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void recvTimingSnoopReq(PacketPtr pkt);
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/**
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* Handle a snoop response.
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* @param pkt Snoop response packet
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*/
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void recvTimingSnoopResp(PacketPtr pkt);
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/**
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* Performs the access specified by the request.
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* @param pkt The request to perform.
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* @return The number of ticks required for the access.
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*/
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Tick recvAtomic(PacketPtr pkt);
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/**
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* Snoop for the provided request in the cache and return the estimated
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* time taken.
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* @param pkt The memory request to snoop
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* @return The number of ticks required for the snoop.
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*/
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Tick recvAtomicSnoop(PacketPtr pkt);
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/**
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* Performs the access specified by the request.
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* @param pkt The request to perform.
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* @param fromCpuSide from the CPU side port or the memory side port
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*/
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void functionalAccess(PacketPtr pkt, bool fromCpuSide);
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/**
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* Perform any necessary updates to the block and perform any data
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* exchange between the packet and the block. The flags of the
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* packet are also set accordingly.
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*
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* @param pkt Request packet from upstream that hit a block
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* @param blk Cache block that the packet hit
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* @param deferred_response Whether this hit is to block that
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* originally missed
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* @param pending_downgrade Whether the writable flag is to be removed
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*
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* @return True if the block is to be invalidated
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*/
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void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
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bool deferred_response = false,
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bool pending_downgrade = false);
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void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
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bool already_copied, bool pending_inval);
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/**
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* Perform an upward snoop if needed, and update the block state
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* (possibly invalidating the block). Also create a response if required.
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*
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* @param pkt Snoop packet
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* @param blk Cache block being snooped
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* @param is_timing Timing or atomic for the response
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* @param is_deferred Is this a deferred snoop or not?
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* @param pending_inval Do we have a pending invalidation?
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*
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* @return The snoop delay incurred by the upwards snoop
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*/
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uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
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bool is_timing, bool is_deferred, bool pending_inval);
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/**
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* Create a writeback request for the given block.
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* @param blk The block to writeback.
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* @return The writeback request for the block.
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*/
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PacketPtr writebackBlk(CacheBlk *blk);
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/**
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* Create a CleanEvict request for the given block.
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* @param blk The block to evict.
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* @return The CleanEvict request for the block.
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*/
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PacketPtr cleanEvictBlk(CacheBlk *blk);
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void memWriteback() override;
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void memInvalidate() override;
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bool isDirty() const override;
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/**
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* Cache block visitor that writes back dirty cache blocks using
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* functional writes.
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*
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* \return Always returns true.
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*/
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bool writebackVisitor(CacheBlk &blk);
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/**
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* Cache block visitor that invalidates all blocks in the cache.
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*
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* @warn Dirty cache lines will not be written back to memory.
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*
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* \return Always returns true.
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*/
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bool invalidateVisitor(CacheBlk &blk);
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/**
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* Create an appropriate downstream bus request packet for the
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* given parameters.
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* @param cpu_pkt The miss that needs to be satisfied.
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* @param blk The block currently in the cache corresponding to
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* cpu_pkt (nullptr if none).
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* @param needsWritable Indicates that the block must be writable
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* even if the request in cpu_pkt doesn't indicate that.
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* @return A new Packet containing the request, or nullptr if the
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* current request in cpu_pkt should just be forwarded on.
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*/
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PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
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bool needsWritable) const;
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/**
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* Return the next queue entry to service, either a pending miss
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* from the MSHR queue, a buffered write from the write buffer, or
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* something from the prefetcher. This function is responsible
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* for prioritizing among those sources on the fly.
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*/
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QueueEntry* getNextQueueEntry();
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/**
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* Send up a snoop request and find cached copies. If cached copies are
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* found, set the BLOCK_CACHED flag in pkt.
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*/
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bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const;
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/**
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* Return whether there are any outstanding misses.
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*/
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bool outstandingMisses() const
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{
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return !mshrQueue.isEmpty();
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}
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CacheBlk *findBlock(Addr addr, bool is_secure) const {
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return tags->findBlock(addr, is_secure);
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}
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bool inCache(Addr addr, bool is_secure) const override {
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return (tags->findBlock(addr, is_secure) != 0);
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}
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bool inMissQueue(Addr addr, bool is_secure) const override {
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return (mshrQueue.findMatch(addr, is_secure) != 0);
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}
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/**
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* Find next request ready time from among possible sources.
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*/
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Tick nextQueueReadyTime() const;
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public:
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/** Instantiates a basic cache object. */
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Cache(const CacheParams *p);
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/** Non-default destructor is needed to deallocate memory. */
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virtual ~Cache();
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void regStats() override;
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/**
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|
* Take an MSHR, turn it into a suitable downstream packet, and
|
|
* send it out. This construct allows a queue entry to choose a suitable
|
|
* approach based on its type.
|
|
*
|
|
* @param mshr The MSHR to turn into a packet and send
|
|
* @return True if the port is waiting for a retry
|
|
*/
|
|
bool sendMSHRQueuePacket(MSHR* mshr);
|
|
|
|
/**
|
|
* Similar to sendMSHR, but for a write-queue entry
|
|
* instead. Create the packet, and send it, and if successful also
|
|
* mark the entry in service.
|
|
*
|
|
* @param wq_entry The write-queue entry to turn into a packet and send
|
|
* @return True if the port is waiting for a retry
|
|
*/
|
|
bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
|
|
|
|
/** serialize the state of the caches
|
|
* We currently don't support checkpointing cache state, so this panics.
|
|
*/
|
|
void serialize(CheckpointOut &cp) const override;
|
|
void unserialize(CheckpointIn &cp) override;
|
|
};
|
|
|
|
/**
|
|
* Wrap a method and present it as a cache block visitor.
|
|
*
|
|
* For example the forEachBlk method in the tag arrays expects a
|
|
* callable object/function as their parameter. This class wraps a
|
|
* method in an object and presents callable object that adheres to
|
|
* the cache block visitor protocol.
|
|
*/
|
|
class CacheBlkVisitorWrapper : public CacheBlkVisitor
|
|
{
|
|
public:
|
|
typedef bool (Cache::*VisitorPtr)(CacheBlk &blk);
|
|
|
|
CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
|
|
: cache(_cache), visitor(_visitor) {}
|
|
|
|
bool operator()(CacheBlk &blk) override {
|
|
return (cache.*visitor)(blk);
|
|
}
|
|
|
|
private:
|
|
Cache &cache;
|
|
VisitorPtr visitor;
|
|
};
|
|
|
|
/**
|
|
* Cache block visitor that determines if there are dirty blocks in a
|
|
* cache.
|
|
*
|
|
* Use with the forEachBlk method in the tag array to determine if the
|
|
* array contains dirty blocks.
|
|
*/
|
|
class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
|
|
{
|
|
public:
|
|
CacheBlkIsDirtyVisitor()
|
|
: _isDirty(false) {}
|
|
|
|
bool operator()(CacheBlk &blk) override {
|
|
if (blk.isDirty()) {
|
|
_isDirty = true;
|
|
return false;
|
|
} else {
|
|
return true;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Does the array contain a dirty line?
|
|
*
|
|
* \return true if yes, false otherwise.
|
|
*/
|
|
bool isDirty() const { return _isDirty; };
|
|
|
|
private:
|
|
bool _isDirty;
|
|
};
|
|
|
|
#endif // __MEM_CACHE_CACHE_HH__
|