739 lines
24 KiB
Text
739 lines
24 KiB
Text
/*
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* Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Blake Hechtman
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*/
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machine(MachineType:TCC, "TCC Cache")
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: CacheMemory * L2cache;
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bool WB; /*is this cache Writeback?*/
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Cycles l2_request_latency := 50;
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Cycles l2_response_latency := 20;
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// From the TCPs or SQCs
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MessageBuffer * requestFromTCP, network="From", virtual_network="1", vnet_type="request";
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// To the Cores. TCC deals only with TCPs/SQCs.
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MessageBuffer * responseToCore, network="To", virtual_network="3", vnet_type="response";
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// From the NB
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MessageBuffer * probeFromNB, network="From", virtual_network="0", vnet_type="request";
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MessageBuffer * responseFromNB, network="From", virtual_network="2", vnet_type="response";
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// To the NB
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MessageBuffer * requestToNB, network="To", virtual_network="0", vnet_type="request";
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MessageBuffer * responseToNB, network="To", virtual_network="2", vnet_type="response";
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MessageBuffer * unblockToNB, network="To", virtual_network="4", vnet_type="unblock";
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MessageBuffer * triggerQueue;
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{
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// EVENTS
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enumeration(Event, desc="TCC Events") {
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// Requests coming from the Cores
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RdBlk, desc="RdBlk event";
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WrVicBlk, desc="L1 Write Through";
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WrVicBlkBack, desc="L1 Write Through(dirty cache)";
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Atomic, desc="Atomic Op";
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AtomicDone, desc="AtomicOps Complete";
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AtomicNotDone, desc="AtomicOps not Complete";
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Data, desc="data messgae";
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// Coming from this TCC
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L2_Repl, desc="L2 Replacement";
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// Probes
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PrbInv, desc="Invalidating probe";
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// Coming from Memory Controller
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WBAck, desc="writethrough ack from memory";
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}
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// STATES
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state_declaration(State, desc="TCC State", default="TCC_State_I") {
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M, AccessPermission:Read_Write, desc="Modified(dirty cache only)";
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W, AccessPermission:Read_Write, desc="Written(dirty cache only)";
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V, AccessPermission:Read_Only, desc="Valid";
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I, AccessPermission:Invalid, desc="Invalid";
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IV, AccessPermission:Busy, desc="Waiting for Data";
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WI, AccessPermission:Busy, desc="Waiting on Writethrough Ack";
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A, AccessPermission:Busy, desc="Invalid waiting on atomici Data";
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}
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enumeration(RequestType, desc="To communicate stats from transitions to recordStats") {
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DataArrayRead, desc="Read the data array";
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DataArrayWrite, desc="Write the data array";
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TagArrayRead, desc="Read the data array";
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TagArrayWrite, desc="Write the data array";
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}
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// STRUCTURES
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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bool Dirty, desc="Is the data dirty (diff from memory?)";
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DataBlock DataBlk, desc="Data for the block";
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WriteMask writeMask, desc="Dirty byte mask";
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}
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="data for the block";
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bool Dirty, desc="Is the data dirty?";
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bool Shared, desc="Victim hit by shared probe";
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MachineID From, desc="Waiting for writeback from...";
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NetDest Destination, desc="Data destination";
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int numAtomics, desc="number remaining atomics";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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}
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TBETable TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
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void set_cache_entry(AbstractCacheEntry b);
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void unset_cache_entry();
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void set_tbe(TBE b);
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void unset_tbe();
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void wakeUpAllBuffers();
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void wakeUpBuffers(Addr a);
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// FUNCTION DEFINITIONS
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Tick clockEdge();
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Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
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return static_cast(Entry, "pointer", L2cache.lookup(addr));
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}
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DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
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return getCacheEntry(addr).DataBlk;
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}
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bool presentOrAvail(Addr addr) {
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return L2cache.isTagPresent(addr) || L2cache.cacheAvail(addr);
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}
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State getState(TBE tbe, Entry cache_entry, Addr addr) {
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if (is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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return State:I;
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}
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void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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}
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}
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void functionalRead(Addr addr, Packet *pkt) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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testAndRead(addr, tbe.DataBlk, pkt);
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} else {
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functionalMemoryRead(pkt);
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}
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}
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int functionalWrite(Addr addr, Packet *pkt) {
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int num_functional_writes := 0;
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, tbe.DataBlk, pkt);
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}
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num_functional_writes := num_functional_writes +
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functionalMemoryWrite(pkt);
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return num_functional_writes;
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}
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AccessPermission getAccessPermission(Addr addr) {
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TBE tbe := TBEs.lookup(addr);
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if(is_valid(tbe)) {
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return TCC_State_to_permission(tbe.TBEState);
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}
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Entry cache_entry := getCacheEntry(addr);
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if(is_valid(cache_entry)) {
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return TCC_State_to_permission(cache_entry.CacheState);
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}
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return AccessPermission:NotPresent;
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}
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void setAccessPermission(Entry cache_entry, Addr addr, State state) {
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if (is_valid(cache_entry)) {
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cache_entry.changePermission(TCC_State_to_permission(state));
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}
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}
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void recordRequestType(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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L2cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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L2cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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L2cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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L2cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
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}
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}
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bool checkResourceAvailable(RequestType request_type, Addr addr) {
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if (request_type == RequestType:DataArrayRead) {
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return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:DataArrayWrite) {
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return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
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} else if (request_type == RequestType:TagArrayRead) {
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return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else if (request_type == RequestType:TagArrayWrite) {
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return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
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} else {
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error("Invalid RequestType type in checkResourceAvailable");
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return true;
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}
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}
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// ** OUT_PORTS **
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// Three classes of ports
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// Class 1: downward facing network links to NB
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out_port(requestToNB_out, CPURequestMsg, requestToNB);
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out_port(responseToNB_out, ResponseMsg, responseToNB);
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out_port(unblockToNB_out, UnblockMsg, unblockToNB);
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// Class 2: upward facing ports to GPU cores
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out_port(responseToCore_out, ResponseMsg, responseToCore);
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out_port(triggerQueue_out, TriggerMsg, triggerQueue);
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//
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// request queue going to NB
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//
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// ** IN_PORTS **
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in_port(triggerQueue_in, TiggerMsg, triggerQueue) {
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if (triggerQueue_in.isReady(clockEdge())) {
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peek(triggerQueue_in, TriggerMsg) {
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TBE tbe := TBEs.lookup(in_msg.addr);
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Entry cache_entry := getCacheEntry(in_msg.addr);
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if (tbe.numAtomics == 0) {
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trigger(Event:AtomicDone, in_msg.addr, cache_entry, tbe);
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} else {
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trigger(Event:AtomicNotDone, in_msg.addr, cache_entry, tbe);
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}
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}
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}
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}
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in_port(responseFromNB_in, ResponseMsg, responseFromNB) {
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if (responseFromNB_in.isReady(clockEdge())) {
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peek(responseFromNB_in, ResponseMsg, block_on="addr") {
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TBE tbe := TBEs.lookup(in_msg.addr);
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Entry cache_entry := getCacheEntry(in_msg.addr);
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if (in_msg.Type == CoherenceResponseType:NBSysResp) {
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if(presentOrAvail(in_msg.addr)) {
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trigger(Event:Data, in_msg.addr, cache_entry, tbe);
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} else {
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Addr victim := L2cache.cacheProbe(in_msg.addr);
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trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
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}
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} else if (in_msg.Type == CoherenceResponseType:NBSysWBAck) {
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trigger(Event:WBAck, in_msg.addr, cache_entry, tbe);
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} else {
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error("Unexpected Response Message to Core");
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}
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}
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}
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}
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// Finally handling incoming requests (from TCP) and probes (from NB).
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in_port(probeNetwork_in, NBProbeRequestMsg, probeFromNB) {
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if (probeNetwork_in.isReady(clockEdge())) {
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peek(probeNetwork_in, NBProbeRequestMsg) {
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DPRINTF(RubySlicc, "%s\n", in_msg);
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs.lookup(in_msg.addr);
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trigger(Event:PrbInv, in_msg.addr, cache_entry, tbe);
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}
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}
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}
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in_port(coreRequestNetwork_in, CPURequestMsg, requestFromTCP, rank=0) {
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if (coreRequestNetwork_in.isReady(clockEdge())) {
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peek(coreRequestNetwork_in, CPURequestMsg) {
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TBE tbe := TBEs.lookup(in_msg.addr);
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Entry cache_entry := getCacheEntry(in_msg.addr);
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if (in_msg.Type == CoherenceRequestType:WriteThrough) {
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if(WB) {
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if(presentOrAvail(in_msg.addr)) {
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trigger(Event:WrVicBlkBack, in_msg.addr, cache_entry, tbe);
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} else {
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Addr victim := L2cache.cacheProbe(in_msg.addr);
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trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
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}
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} else {
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trigger(Event:WrVicBlk, in_msg.addr, cache_entry, tbe);
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}
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} else if (in_msg.Type == CoherenceRequestType:Atomic) {
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trigger(Event:Atomic, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:RdBlk) {
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trigger(Event:RdBlk, in_msg.addr, cache_entry, tbe);
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} else {
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DPRINTF(RubySlicc, "%s\n", in_msg);
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error("Unexpected Response Message to Core");
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}
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}
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}
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}
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// BEGIN ACTIONS
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action(i_invL2, "i", desc="invalidate TCC cache block") {
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if (is_valid(cache_entry)) {
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L2cache.deallocate(address);
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}
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unset_cache_entry();
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}
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action(sd_sendData, "sd", desc="send Shared response") {
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peek(coreRequestNetwork_in, CPURequestMsg) {
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enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:TDSysResp;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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out_msg.Dirty := false;
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out_msg.State := CoherenceState:Shared;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(sdr_sendDataResponse, "sdr", desc="send Shared response") {
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enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:TDSysResp;
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out_msg.Sender := machineID;
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out_msg.Destination := tbe.Destination;
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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out_msg.Dirty := false;
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out_msg.State := CoherenceState:Shared;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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enqueue(unblockToNB_out, UnblockMsg, 1) {
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out_msg.addr := address;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Unblock_Control;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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action(rd_requestData, "r", desc="Miss in L2, pass on") {
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if(tbe.Destination.count()==1){
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peek(coreRequestNetwork_in, CPURequestMsg) {
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enqueue(requestToNB_out, CPURequestMsg, l2_request_latency) {
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out_msg.addr := address;
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out_msg.Type := in_msg.Type;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.Shared := false; // unneeded for this request
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out_msg.MessageSize := in_msg.MessageSize;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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}
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action(w_sendResponseWBAck, "w", desc="send WB Ack") {
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peek(responseFromNB_in, ResponseMsg) {
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enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:TDSysWBAck;
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out_msg.Destination.clear();
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out_msg.Destination.add(in_msg.WTRequestor);
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out_msg.Sender := machineID;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(swb_sendWBAck, "swb", desc="send WB Ack") {
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peek(coreRequestNetwork_in, CPURequestMsg) {
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enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:TDSysWBAck;
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out_msg.Destination.clear();
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.Sender := machineID;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(ar_sendAtomicResponse, "ar", desc="send Atomic Ack") {
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peek(responseFromNB_in, ResponseMsg) {
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enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:TDSysResp;
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out_msg.Destination.add(in_msg.WTRequestor);
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out_msg.Sender := machineID;
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out_msg.MessageSize := in_msg.MessageSize;
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out_msg.DataBlk := in_msg.DataBlk;
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}
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}
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}
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action(a_allocateBlock, "a", desc="allocate TCC block") {
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if (is_invalid(cache_entry)) {
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set_cache_entry(L2cache.allocate(address, new Entry));
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cache_entry.writeMask.clear();
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}
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}
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action(t_allocateTBE, "t", desc="allocate TBE Entry") {
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if (is_invalid(tbe)) {
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check_allocate(TBEs);
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TBEs.allocate(address);
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set_tbe(TBEs.lookup(address));
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tbe.Destination.clear();
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tbe.numAtomics := 0;
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}
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if (coreRequestNetwork_in.isReady(clockEdge())) {
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peek(coreRequestNetwork_in, CPURequestMsg) {
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if(in_msg.Type == CoherenceRequestType:RdBlk || in_msg.Type == CoherenceRequestType:Atomic){
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tbe.Destination.add(in_msg.Requestor);
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}
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}
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}
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}
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action(dt_deallocateTBE, "dt", desc="Deallocate TBE entry") {
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tbe.Destination.clear();
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TBEs.deallocate(address);
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unset_tbe();
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}
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action(wcb_writeCacheBlock, "wcb", desc="write data to TCC") {
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peek(responseFromNB_in, ResponseMsg) {
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cache_entry.DataBlk := in_msg.DataBlk;
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DPRINTF(RubySlicc, "Writing to TCC: %s\n", in_msg);
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}
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}
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action(wdb_writeDirtyBytes, "wdb", desc="write data to TCC") {
|
|
peek(coreRequestNetwork_in, CPURequestMsg) {
|
|
cache_entry.DataBlk.copyPartial(in_msg.DataBlk,in_msg.writeMask);
|
|
cache_entry.writeMask.orMask(in_msg.writeMask);
|
|
DPRINTF(RubySlicc, "Writing to TCC: %s\n", in_msg);
|
|
}
|
|
}
|
|
|
|
action(wt_writeThrough, "wt", desc="write back data") {
|
|
peek(coreRequestNetwork_in, CPURequestMsg) {
|
|
enqueue(requestToNB_out, CPURequestMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.WTRequestor := in_msg.Requestor;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Data;
|
|
out_msg.Type := CoherenceRequestType:WriteThrough;
|
|
out_msg.Dirty := true;
|
|
out_msg.DataBlk := in_msg.DataBlk;
|
|
out_msg.writeMask.orMask(in_msg.writeMask);
|
|
}
|
|
}
|
|
}
|
|
|
|
action(wb_writeBack, "wb", desc="write back data") {
|
|
enqueue(requestToNB_out, CPURequestMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.WTRequestor := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Data;
|
|
out_msg.Type := CoherenceRequestType:WriteThrough;
|
|
out_msg.Dirty := true;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.writeMask.orMask(cache_entry.writeMask);
|
|
}
|
|
}
|
|
|
|
action(at_atomicThrough, "at", desc="write back data") {
|
|
peek(coreRequestNetwork_in, CPURequestMsg) {
|
|
enqueue(requestToNB_out, CPURequestMsg, l2_request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.WTRequestor := in_msg.Requestor;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Data;
|
|
out_msg.Type := CoherenceRequestType:Atomic;
|
|
out_msg.Dirty := true;
|
|
out_msg.writeMask.orMask(in_msg.writeMask);
|
|
}
|
|
}
|
|
}
|
|
|
|
action(pi_sendProbeResponseInv, "pi", desc="send probe ack inv, no data") {
|
|
enqueue(responseToNB_out, ResponseMsg, 1) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := CoherenceResponseType:CPUPrbResp; // TCC, L3 respond in same way to probes
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.Dirty := false;
|
|
out_msg.Hit := false;
|
|
out_msg.Ntsl := true;
|
|
out_msg.State := CoherenceState:NA;
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
}
|
|
}
|
|
action(ut_updateTag, "ut", desc="update Tag (i.e. set MRU)") {
|
|
L2cache.setMRU(address);
|
|
}
|
|
|
|
action(p_popRequestQueue, "p", desc="pop request queue") {
|
|
coreRequestNetwork_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(pr_popResponseQueue, "pr", desc="pop response queue") {
|
|
responseFromNB_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(pp_popProbeQueue, "pp", desc="pop probe queue") {
|
|
probeNetwork_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(z_stall, "z", desc="stall") {
|
|
// built-in
|
|
}
|
|
|
|
|
|
action(ina_incrementNumAtomics, "ina", desc="inc num atomics") {
|
|
tbe.numAtomics := tbe.numAtomics + 1;
|
|
}
|
|
|
|
|
|
action(dna_decrementNumAtomics, "dna", desc="inc num atomics") {
|
|
tbe.numAtomics := tbe.numAtomics - 1;
|
|
if (tbe.numAtomics==0) {
|
|
enqueue(triggerQueue_out, TriggerMsg, 1) {
|
|
out_msg.addr := address;
|
|
out_msg.Type := TriggerType:AtomicDone;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(ptr_popTriggerQueue, "ptr", desc="pop Trigger") {
|
|
triggerQueue_in.dequeue(clockEdge());
|
|
}
|
|
|
|
// END ACTIONS
|
|
|
|
// BEGIN TRANSITIONS
|
|
// transitions from base
|
|
// Assumptions for ArrayRead/Write
|
|
// TBE checked before tags
|
|
// Data Read/Write requires Tag Read
|
|
|
|
// Stalling transitions do NOT check the tag array...and if they do,
|
|
// they can cause a resource stall deadlock!
|
|
|
|
transition(WI, {RdBlk, WrVicBlk, Atomic, WrVicBlkBack}) { //TagArrayRead} {
|
|
z_stall;
|
|
}
|
|
transition(A, {RdBlk, WrVicBlk, WrVicBlkBack}) { //TagArrayRead} {
|
|
z_stall;
|
|
}
|
|
transition(IV, {WrVicBlk, Atomic, WrVicBlkBack}) { //TagArrayRead} {
|
|
z_stall;
|
|
}
|
|
transition({M, V}, RdBlk) {TagArrayRead, DataArrayRead} {
|
|
sd_sendData;
|
|
ut_updateTag;
|
|
p_popRequestQueue;
|
|
}
|
|
transition(W, RdBlk, WI) {TagArrayRead, DataArrayRead} {
|
|
t_allocateTBE;
|
|
wb_writeBack;
|
|
}
|
|
|
|
transition(I, RdBlk, IV) {TagArrayRead} {
|
|
t_allocateTBE;
|
|
rd_requestData;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition(IV, RdBlk) {
|
|
t_allocateTBE;
|
|
rd_requestData;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition({V, I},Atomic, A) {TagArrayRead} {
|
|
i_invL2;
|
|
t_allocateTBE;
|
|
at_atomicThrough;
|
|
ina_incrementNumAtomics;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition(A, Atomic) {
|
|
at_atomicThrough;
|
|
ina_incrementNumAtomics;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition({M, W}, Atomic, WI) {TagArrayRead} {
|
|
t_allocateTBE;
|
|
wb_writeBack;
|
|
}
|
|
|
|
transition(I, WrVicBlk) {TagArrayRead} {
|
|
wt_writeThrough;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition(V, WrVicBlk) {TagArrayRead, DataArrayWrite} {
|
|
ut_updateTag;
|
|
wdb_writeDirtyBytes;
|
|
wt_writeThrough;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition({V, M}, WrVicBlkBack, M) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
|
|
ut_updateTag;
|
|
swb_sendWBAck;
|
|
wdb_writeDirtyBytes;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition(W, WrVicBlkBack) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
|
|
ut_updateTag;
|
|
swb_sendWBAck;
|
|
wdb_writeDirtyBytes;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition(I, WrVicBlkBack, W) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
|
|
a_allocateBlock;
|
|
ut_updateTag;
|
|
swb_sendWBAck;
|
|
wdb_writeDirtyBytes;
|
|
p_popRequestQueue;
|
|
}
|
|
|
|
transition({W, M}, L2_Repl, WI) {TagArrayRead, DataArrayRead} {
|
|
t_allocateTBE;
|
|
wb_writeBack;
|
|
i_invL2;
|
|
}
|
|
|
|
transition({I, V}, L2_Repl, I) {TagArrayRead, TagArrayWrite} {
|
|
i_invL2;
|
|
}
|
|
|
|
transition({A, IV, WI}, L2_Repl) {
|
|
i_invL2;
|
|
}
|
|
|
|
transition({I, V}, PrbInv, I) {TagArrayRead, TagArrayWrite} {
|
|
pi_sendProbeResponseInv;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(M, PrbInv, W) {TagArrayRead, TagArrayWrite} {
|
|
pi_sendProbeResponseInv;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(W, PrbInv) {TagArrayRead} {
|
|
pi_sendProbeResponseInv;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition({A, IV, WI}, PrbInv) {
|
|
pi_sendProbeResponseInv;
|
|
pp_popProbeQueue;
|
|
}
|
|
|
|
transition(IV, Data, V) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
|
|
a_allocateBlock;
|
|
ut_updateTag;
|
|
wcb_writeCacheBlock;
|
|
sdr_sendDataResponse;
|
|
pr_popResponseQueue;
|
|
dt_deallocateTBE;
|
|
}
|
|
|
|
transition(A, Data) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
|
|
a_allocateBlock;
|
|
ar_sendAtomicResponse;
|
|
dna_decrementNumAtomics;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(A, AtomicDone, I) {TagArrayRead, TagArrayWrite} {
|
|
dt_deallocateTBE;
|
|
ptr_popTriggerQueue;
|
|
}
|
|
|
|
transition(A, AtomicNotDone) {TagArrayRead} {
|
|
ptr_popTriggerQueue;
|
|
}
|
|
|
|
//M,W should not see WBAck as the cache is in WB mode
|
|
//WBAcks do not need to check tags
|
|
transition({I, V, IV, A}, WBAck) {
|
|
w_sendResponseWBAck;
|
|
pr_popResponseQueue;
|
|
}
|
|
|
|
transition(WI, WBAck,I) {
|
|
dt_deallocateTBE;
|
|
pr_popResponseQueue;
|
|
}
|
|
}
|