320 lines
9.4 KiB
C++
320 lines
9.4 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2015 RISC-V Foundation
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// Copyright (c) 2016 The University of Virginia
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Alec Roelke
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////////////////////////////////////////////////////////////////////
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//
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// Integer instructions
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//
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output header {{
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#include <iostream>
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/**
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* Base class for R-type operations
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*/
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class ROp : public RiscvStaticInst
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{
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protected:
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/// Constructor
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ROp(const char *mnem, MachInst _machInst, OpClass __opClass)
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: RiscvStaticInst(mnem, _machInst, __opClass)
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{}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for I-type operations
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*/
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class IOp : public RiscvStaticInst
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{
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protected:
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int64_t imm;
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/// Constructor
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IOp(const char *mnem, MachInst _machInst, OpClass __opClass)
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: RiscvStaticInst(mnem, _machInst, __opClass),imm(IMM12)
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{
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if (IMMSIGN > 0)
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imm |= ~((uint64_t)0x7FF);
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Class for jalr instructions
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*/
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class Jump : public IOp
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{
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protected:
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Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
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: IOp(mnem, _machInst, __opClass)
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{}
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RiscvISA::PCState
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branchTarget(ThreadContext *tc) const;
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using StaticInst::branchTarget;
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using IOp::generateDisassembly;
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};
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/**
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* Base class for S-type operations
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*/
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class SOp : public RiscvStaticInst
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{
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protected:
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int64_t imm;
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/// Constructor
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SOp(const char *mnem, MachInst _machInst, OpClass __opClass)
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: RiscvStaticInst(mnem, _machInst, __opClass),imm(0)
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{
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imm |= IMM5;
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imm |= IMM7 << 5;
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if (IMMSIGN > 0)
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imm |= ~((uint64_t)0x7FF);
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for SB-type operations
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*/
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class SBOp : public RiscvStaticInst
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{
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protected:
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int64_t imm;
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/// Constructor
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SBOp(const char *mnem, MachInst _machInst, OpClass __opClass)
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: RiscvStaticInst(mnem, _machInst, __opClass),imm(0)
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{
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imm |= BIMM12BIT11 << 11;
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imm |= BIMM12BITS4TO1 << 1;
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imm |= BIMM12BITS10TO5 << 5;
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if (IMMSIGN > 0)
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imm |= ~((uint64_t)0xFFF);
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}
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RiscvISA::PCState
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branchTarget(const RiscvISA::PCState &branchPC) const;
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using StaticInst::branchTarget;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for U-type operations
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*/
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class UOp : public RiscvStaticInst
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{
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protected:
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int64_t imm;
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/// Constructor
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UOp(const char *mnem, MachInst _machInst, OpClass __opClass)
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: RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
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{
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int32_t temp = IMM20 << 12;
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imm = temp;
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for UJ-type operations
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*/
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class UJOp : public RiscvStaticInst
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{
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protected:
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int64_t imm;
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/// Constructor
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UJOp(const char *mnem, MachInst _machInst, OpClass __opClass)
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: RiscvStaticInst(mnem, _machInst, __opClass),imm(0)
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{
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imm |= UJIMMBITS19TO12 << 12;
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imm |= UJIMMBIT11 << 11;
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imm |= UJIMMBITS10TO1 << 1;
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if (IMMSIGN > 0)
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imm |= ~((uint64_t)0xFFFFF);
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}
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RiscvISA::PCState
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branchTarget(const RiscvISA::PCState &branchPC) const;
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using StaticInst::branchTarget;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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//Outputs to decoder.cc
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output decoder {{
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std::string
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ROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " <<
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regName(_srcRegIdx[0]) << ", " << regName(_srcRegIdx[1]);
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return ss.str();
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}
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std::string
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IOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " <<
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regName(_srcRegIdx[0]) << ", " << imm;
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return ss.str();
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}
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RiscvISA::PCState
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Jump::branchTarget(ThreadContext *tc) const
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{
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PCState pc = tc->pcState();
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IntReg Rs1 = tc->readIntReg(_srcRegIdx[0]);
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pc.set((Rs1 + imm)&~0x1);
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return pc;
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}
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std::string
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SOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ss << mnemonic << ' ' << regName(_srcRegIdx[1]) << ", " << imm <<
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'(' << regName(_srcRegIdx[0]) << ')';
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return ss.str();
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}
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RiscvISA::PCState
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SBOp::branchTarget(const RiscvISA::PCState &branchPC) const
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{
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return branchPC.pc() + imm;
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}
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std::string
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SBOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ss << mnemonic << ' ' << regName(_srcRegIdx[0]) << ", " <<
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regName(_srcRegIdx[1]) << ", " << imm;
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return ss.str();
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}
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std::string
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UOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << imm;
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return ss.str();
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}
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RiscvISA::PCState
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UJOp::branchTarget(const RiscvISA::PCState &branchPC) const
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{
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return branchPC.pc() + imm;
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}
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std::string
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UJOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << imm;
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return ss.str();
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}
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}};
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def format ROp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'ROp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format IOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'IOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format Jump(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'Jump', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format SOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'SOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format SBOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'SBOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format UOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'UOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format UJOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'UJOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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