356 lines
9.3 KiB
C++
356 lines
9.3 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2015 RISC-V Foundation
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// Copyright (c) 2016 The University of Virginia
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Alec Roelke
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////////////////////////////////////////////////////////////////////
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//
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// Memory operation instructions
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//
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output header {{
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class Load : public RiscvStaticInst
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{
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public:
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/// Displacement for EA calculation (signed).
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int64_t ldisp;
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protected:
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/// Memory request flags. See mem_req_base.hh.
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Request::Flags memAccessFlags;
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/// Constructor
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Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
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: RiscvStaticInst(mnem, _machInst, __opClass), ldisp(IMM12)
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{
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if (IMMSIGN > 0)
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ldisp |= ~((uint64_t)0xFFF);
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class Store : public RiscvStaticInst
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{
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public:
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/// Displacement for EA calculation (signed).
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int64_t sdisp;
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protected:
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/// Memory request flags. See mem_req_base.hh.
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Request::Flags memAccessFlags;
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/// Constructor
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Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
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: RiscvStaticInst(mnem, _machInst, __opClass), sdisp(IMM5)
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{
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sdisp |= IMM7 << 5;
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if (IMMSIGN > 0)
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sdisp |= ~((uint64_t)0xFFF);
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << ldisp <<
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'(' << regName(_srcRegIdx[0]) << ')';
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return ss.str();
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}
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std::string
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Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ss << mnemonic << ' ' << regName(_srcRegIdx[1]) << ", " << sdisp <<
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'(' << regName(_srcRegIdx[0]) << ')';
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return ss.str();
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}
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}};
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def template LoadStoreDeclare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst);
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%(BasicExecDeclare)s
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%(EACompDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template EACompDeclare {{
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Fault
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eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template InitiateAccDeclare {{
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Fault
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initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template CompleteAccDeclare {{
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Fault
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completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template LoadStoreConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst):
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%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
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{
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%(constructor)s;
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}
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}};
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def template EACompExecute {{
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Fault
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%(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(op_wb)s;
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xc->setEA(EA);
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}
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return fault;
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}
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}};
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let {{
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def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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base_class, postacc_code='', decode_template=BasicDecode,
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exec_template_base=''):
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# Make sure flags are in lists (convert to lists if not).
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mem_flags = makeList(mem_flags)
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inst_flags = makeList(inst_flags) # + ['IsNonSpeculative']
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iop = InstObjParams(name, Name, base_class,
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{ 'ea_code':ea_code, 'memacc_code':memacc_code,
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'postacc_code':postacc_code }, inst_flags)
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if mem_flags:
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mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
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s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
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iop.constructor += s
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# select templates
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fullExecTemplate = eval(exec_template_base + 'Execute')
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initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
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completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
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# (header_output, decoder_output, decode_block, exec_output)
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return (LoadStoreDeclare.subst(iop),
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LoadStoreConstructor.subst(iop),
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decode_template.subst(iop),
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fullExecTemplate.subst(iop) +
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EACompExecute.subst(iop) +
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initiateAccTemplate.subst(iop) +
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completeAccTemplate.subst(iop))
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}};
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def template LoadExecute {{
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Fault
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%(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template LoadInitiateAcc {{
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Fault
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%(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_src_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
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}
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return fault;
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}
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}};
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def template LoadCompleteAcc {{
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Fault
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%(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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getMem(pkt, Mem, traceData);
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreExecute {{
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Fault
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%(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
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nullptr);
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreInitiateAcc {{
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Fault
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%(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemTiming(xc, traceData, Mem, EA,
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memAccessFlags, nullptr);
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreCompleteAcc {{
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Fault
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%(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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return NoFault;
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}
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}};
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def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
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inst_flags=[]) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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'Load', exec_template_base='Load')
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}};
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def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
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inst_flags=[]) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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'Store', exec_template_base='Store')
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}};
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