333 lines
9.7 KiB
C++
333 lines
9.7 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2015 RISC-V Foundation
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// Copyright (c) 2016 The University of Virginia
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Alec Roelke
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////////////////////////////////////////////////////////////////////
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//
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// The RISC-V ISA decoder
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//
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decode OPCODE default Unknown::unknown() {
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0x03: decode FUNCT3 {
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format Load {
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0x0: lb({{
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Rd_sd = Mem_sb;
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}});
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0x1: lh({{
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Rd_sd = Mem_sh;
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}});
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0x2: lw({{
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Rd_sd = Mem_sw;
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}});
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0x3: ld({{
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Rd_sd = Mem_sd;
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}});
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0x4: lbu({{
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Rd = Mem_ub;
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}});
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0x5: lhu({{
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Rd = Mem_uh;
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}});
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0x6: lwu({{
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Rd = Mem_uw;
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}});
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}
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}
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0x0f: decode FUNCT3 {
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format IOp {
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0x0: fence({{
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}}, IsNonSpeculative, IsMemBarrier, No_OpClass);
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0x1: fence_i({{
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}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
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}
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}
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0x13: decode FUNCT3 {
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format IOp {
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0x0: addi({{
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Rd_sd = Rs1_sd + imm;
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}});
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0x1: slli({{
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Rd = Rs1 << SHAMT6;
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}});
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0x2: slti({{
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Rd = (Rs1_sd < imm) ? 1 : 0;
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}});
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0x3: sltiu({{
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Rd = (Rs1 < (uint64_t)imm) ? 1 : 0;
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}});
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0x4: xori({{
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Rd = Rs1 ^ (uint64_t)imm;
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}});
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0x5: decode SRTYPE {
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0x0: srli({{
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Rd = Rs1 >> SHAMT6;
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}});
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0x1: srai({{
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Rd_sd = Rs1_sd >> SHAMT6;
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}});
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}
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0x6: ori({{
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Rd = Rs1 | (uint64_t)imm;
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}});
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0x7: andi({{
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Rd = Rs1 & (uint64_t)imm;
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}});
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}
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}
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0x17: UOp::auipc({{
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Rd = PC + imm;
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}});
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0x1b: decode FUNCT3 {
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format IOp {
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0x0: addiw({{
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Rd_sd = (int32_t)Rs1 + (int32_t)imm;
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}});
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0x1: slliw({{
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Rd_sd = Rs1_sw << SHAMT5;
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}});
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0x5: decode SRTYPE {
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0x0: srliw({{
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Rd = Rs1_uw >> SHAMT5;
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}});
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0x1: sraiw({{
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Rd_sd = Rs1_sw >> SHAMT5;
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}});
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}
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}
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}
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0x23: decode FUNCT3 {
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format Store {
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0x0: sb({{
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Mem_ub = Rs2_ub;
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}});
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0x1: sh({{
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Mem_uh = Rs2_uh;
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}});
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0x2: sw({{
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Mem_uw = Rs2_uw;
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}});
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0x3: sd({{
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Mem_ud = Rs2_ud;
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}});
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}
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}
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0x33: decode FUNCT3 {
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format ROp {
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0x0: decode FUNCT7 {
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0x0: add({{
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Rd = Rs1_sd + Rs2_sd;
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}});
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0x20: sub({{
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Rd = Rs1_sd - Rs2_sd;
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}});
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}
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0x1: decode FUNCT7 {
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0x0: sll({{
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Rd = Rs1 << Rs2<5:0>;
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}});
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}
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0x2: decode FUNCT7 {
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0x0: slt({{
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Rd = (Rs1_sd < Rs2_sd) ? 1 : 0;
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}});
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}
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0x3: decode FUNCT7 {
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0x0: sltu({{
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Rd = (Rs1 < Rs2) ? 1 : 0;
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}});
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}
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0x4: decode FUNCT7 {
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0x0: xor({{
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Rd = Rs1 ^ Rs2;
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}});
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}
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0x5: decode FUNCT7 {
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0x0: srl({{
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Rd = Rs1 >> Rs2<5:0>;
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}});
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0x20: sra({{
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Rd_sd = Rs1_sd >> Rs2<5:0>;
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}});
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}
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0x6: decode FUNCT7 {
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0x0: or({{
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Rd = Rs1 | Rs2;
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}});
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}
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0x7: decode FUNCT7 {
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0x0: and({{
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Rd = Rs1 & Rs2;
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}});
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}
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}
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}
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0x37: UOp::lui({{
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Rd = (uint64_t)imm;
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}});
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0x3b: decode FUNCT3 {
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format ROp {
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0x0: decode FUNCT7 {
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0x0: addw({{
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Rd_sd = Rs1_sw + Rs2_sw;
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}});
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0x20: subw({{
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Rd_sd = Rs1_sw - Rs2_sw;
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}});
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}
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0x1: sllw({{
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Rd_sd = Rs1_sw << Rs2<4:0>;
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}});
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0x5: decode FUNCT7 {
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0x0: srlw({{
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Rd_uw = Rs1_uw >> Rs2<4:0>;
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}});
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0x20: sraw({{
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Rd_sd = Rs1_sw >> Rs2<4:0>;
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}});
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}
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}
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}
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0x63: decode FUNCT3 {
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format SBOp {
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0x0: beq({{
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if (Rs1 == Rs2) {
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NPC = PC + imm;
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} else {
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NPC = NPC;
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}
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}}, IsDirectControl, IsCondControl);
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0x1: bne({{
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if (Rs1 != Rs2) {
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NPC = PC + imm;
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} else {
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NPC = NPC;
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}
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}}, IsDirectControl, IsCondControl);
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0x4: blt({{
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if (Rs1_sd < Rs2_sd) {
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NPC = PC + imm;
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} else {
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NPC = NPC;
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}
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}}, IsDirectControl, IsCondControl);
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0x5: bge({{
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if (Rs1_sd >= Rs2_sd) {
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NPC = PC + imm;
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} else {
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NPC = NPC;
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}
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}}, IsDirectControl, IsCondControl);
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0x6: bltu({{
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if (Rs1 < Rs2) {
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NPC = PC + imm;
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} else {
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NPC = NPC;
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}
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}}, IsDirectControl, IsCondControl);
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0x7: bgeu({{
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if (Rs1 >= Rs2) {
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NPC = PC + imm;
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} else {
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NPC = NPC;
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}
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}}, IsDirectControl, IsCondControl);
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}
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}
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0x67: decode FUNCT3 {
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0x0: Jump::jalr({{
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Rd = NPC;
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NPC = (imm + Rs1) & (~0x1);
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}}, IsIndirectControl, IsUncondControl, IsCall);
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}
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0x6f: UJOp::jal({{
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Rd = NPC;
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NPC = PC + imm;
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}}, IsDirectControl, IsUncondControl, IsCall);
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0x73: decode FUNCT3 {
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format IOp {
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0x0: decode FUNCT12 {
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0x0: ecall({{
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fault = std::make_shared<SyscallFault>();
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}}, IsSerializeAfter, IsNonSpeculative, IsSyscall, No_OpClass);
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0x1: ebreak({{
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fault = std::make_shared<BreakpointFault>();
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}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
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0x100: eret({{
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fault = std::make_shared<UnimplementedFault>("eret");
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}}, No_OpClass);
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}
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0x1: csrrw({{
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Rd = xc->readMiscReg(FUNCT12);
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xc->setMiscReg(FUNCT12, Rs1);
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}}, IsNonSpeculative, No_OpClass);
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0x2: csrrs({{
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Rd = xc->readMiscReg(FUNCT12);
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if (Rs1 != 0) {
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xc->setMiscReg(FUNCT12, Rd | Rs1);
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}
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}}, IsNonSpeculative, No_OpClass);
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0x3: csrrc({{
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Rd = xc->readMiscReg(FUNCT12);
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if (Rs1 != 0) {
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xc->setMiscReg(FUNCT12, Rd & ~Rs1);
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}
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}}, IsNonSpeculative, No_OpClass);
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0x5: csrrwi({{
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Rd = xc->readMiscReg(FUNCT12);
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xc->setMiscReg(FUNCT12, ZIMM);
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}}, IsNonSpeculative, No_OpClass);
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0x6: csrrsi({{
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Rd = xc->readMiscReg(FUNCT12);
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if (ZIMM != 0) {
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xc->setMiscReg(FUNCT12, Rd | ZIMM);
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}
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}}, IsNonSpeculative, No_OpClass);
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0x7: csrrci({{
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Rd = xc->readMiscReg(FUNCT12);
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if (ZIMM != 0) {
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xc->setMiscReg(FUNCT12, Rd & ~ZIMM);
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}
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}}, IsNonSpeculative, No_OpClass);
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}
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}
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}
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