80 lines
2.7 KiB
C++
80 lines
2.7 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2015 RISC-V Foundation
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// Copyright (c) 2016 The University of Virginia
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Maxwell Walter
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// Alec Roelke
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////////////////////////////////////////////////////////////////////
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//
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// Base class for Riscv instructions, and some support functions
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//
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//Outputs to decoder.hh
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output header {{
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using namespace RiscvISA;
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/**
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* Base class for all RISC-V static instructions.
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*/
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class RiscvStaticInst : public StaticInst
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{
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protected:
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// Constructor
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RiscvStaticInst(const char *mnem, MachInst _machInst,
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OpClass __opClass) : StaticInst(mnem, _machInst, __opClass)
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{}
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std::string
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regName(RegIndex reg) const;
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virtual std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
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public:
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void
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advancePC(RiscvISA::PCState &pc) const
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{
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pc.advance();
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}
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};
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}};
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//Ouputs to decoder.cc
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output decoder {{
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std::string
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RiscvStaticInst::regName(RegIndex reg) const
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{
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if (reg < FP_Reg_Base) {
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return std::string(RegisterNames[reg]);
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} else {
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return std::string("f") + std::to_string(reg - FP_Reg_Base);
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}
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}
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}};
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