234 lines
7.1 KiB
C++
234 lines
7.1 KiB
C++
/*
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* Copyright (c) 2016 RISC-V Foundation
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* Copyright (c) 2016 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Alec Roelke
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*/
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#include "arch/riscv/isa.hh"
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#include <ctime>
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#include <set>
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#include "arch/riscv/registers.hh"
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#include "base/bitfield.hh"
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#include "cpu/base.hh"
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#include "debug/RiscvMisc.hh"
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#include "params/RiscvISA.hh"
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#include "sim/core.hh"
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#include "sim/pseudo_inst.hh"
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namespace RiscvISA
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{
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std::map<int, std::string> ISA::miscRegNames = {
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{MISCREG_FFLAGS, "fflags"},
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{MISCREG_FRM, "frm"},
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{MISCREG_FCSR, "fcsr"},
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{MISCREG_CYCLE, "cycle"},
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{MISCREG_TIME, "time"},
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{MISCREG_INSTRET, "instret"},
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{MISCREG_CYCLEH, "cycleh"},
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{MISCREG_TIMEH, "timeh"},
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{MISCREG_INSTRETH, "instreth"},
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{MISCREG_SSTATUS, "sstatus"},
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{MISCREG_STVEC, "stvec"},
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{MISCREG_SIE, "sie"},
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{MISCREG_STIMECMP, "stimecmp"},
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{MISCREG_STIME, "stime"},
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{MISCREG_STIMEH, "stimeh"},
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{MISCREG_SSCRATCH, "sscratch"},
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{MISCREG_SEPC, "sepc"},
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{MISCREG_SCAUSE, "scause"},
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{MISCREG_SBADADDR, "sbadaddr"},
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{MISCREG_SIP, "sip"},
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{MISCREG_SPTBR, "sptbr"},
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{MISCREG_SASID, "sasid"},
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{MISCREG_CYCLEW, "cyclew"},
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{MISCREG_TIMEW, "timew"},
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{MISCREG_INSTRETW, "instretw"},
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{MISCREG_CYCLEHW, "cyclehw"},
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{MISCREG_TIMEHW, "timehw"},
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{MISCREG_INSTRETHW, "instrethw"},
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{MISCREG_HSTATUS, "hstatus"},
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{MISCREG_HTVEC, "htvec"},
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{MISCREG_HTDELEG, "htdeleg"},
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{MISCREG_HTIMECMP, "htimecmp"},
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{MISCREG_HTIME, "htime"},
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{MISCREG_HTIMEH, "htimeh"},
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{MISCREG_HSCRATCH, "hscratch"},
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{MISCREG_HEPC, "hepc"},
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{MISCREG_HCAUSE, "hcause"},
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{MISCREG_HBADADDR, "hbadaddr"},
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{MISCREG_STIMEW, "stimew"},
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{MISCREG_STIMEHW, "stimehw"},
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{MISCREG_MCPUID, "mcpuid"},
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{MISCREG_MIMPID, "mimpid"},
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{MISCREG_MHARTID, "mhartid"},
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{MISCREG_MSTATUS, "mstatus"},
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{MISCREG_MTVEC, "mtvec"},
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{MISCREG_MTDELEG, "mtdeleg"},
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{MISCREG_MIE, "mie"},
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{MISCREG_MTIMECMP, "mtimecmp"},
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{MISCREG_MTIME, "mtime"},
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{MISCREG_MTIMEH, "mtimeh"},
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{MISCREG_MSCRATCH, "mscratch"},
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{MISCREG_MEPC, "mepc"},
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{MISCREG_MCAUSE, "mcause"},
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{MISCREG_MBADADDR, "mbadaddr"},
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{MISCREG_MIP, "mip"},
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{MISCREG_MBASE, "mbase"},
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{MISCREG_MBOUND, "mbound"},
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{MISCREG_MIBASE, "mibase"},
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{MISCREG_MIBOUND, "mibound"},
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{MISCREG_MDBASE, "mdbase"},
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{MISCREG_MDBOUND, "mdbound"},
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{MISCREG_HTIMEW, "htimew"},
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{MISCREG_HTIMEHW, "htimehw"},
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{MISCREG_MTOHOST, "mtohost"},
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{MISCREG_MFROMHOST, "mfromhost"}
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};
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ISA::ISA(Params *p) : SimObject(p)
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{
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miscRegFile.resize(NumMiscRegs);
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clear();
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}
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const RiscvISAParams *
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ISA::params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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void ISA::clear()
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{
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std::fill(miscRegFile.begin(), miscRegFile.end(), 0);
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}
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MiscReg
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ISA::readMiscRegNoEffect(int misc_reg) const
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{
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DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n", miscRegNames[misc_reg],
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miscRegFile[misc_reg]);
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switch (misc_reg) {
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case MISCREG_FFLAGS:
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return bits(miscRegFile[MISCREG_FCSR], 4, 0);
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case MISCREG_FRM:
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return bits(miscRegFile[MISCREG_FCSR], 7, 5);
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case MISCREG_FCSR:
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return bits(miscRegFile[MISCREG_FCSR], 31, 0);
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case MISCREG_CYCLE:
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warn("Use readMiscReg to read the cycle CSR.");
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return 0;
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case MISCREG_TIME:
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return std::time(nullptr);
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case MISCREG_INSTRET:
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warn("Use readMiscReg to read the instret CSR.");
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return 0;
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case MISCREG_CYCLEH:
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warn("Use readMiscReg to read the cycleh CSR.");
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return 0;
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case MISCREG_TIMEH:
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return std::time(nullptr) >> 32;
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case MISCREG_INSTRETH:
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warn("Use readMiscReg to read the instreth CSR.");
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return 0;
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default:
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return miscRegFile[misc_reg];
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}
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}
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MiscReg
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ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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{
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switch (misc_reg) {
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case MISCREG_INSTRET:
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DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
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miscRegNames[misc_reg], miscRegFile[misc_reg]);
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return tc->getCpuPtr()->totalInsts();
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case MISCREG_CYCLE:
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DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
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miscRegNames[misc_reg], miscRegFile[misc_reg]);
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return tc->getCpuPtr()->curCycle();
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case MISCREG_INSTRETH:
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DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
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miscRegNames[misc_reg], miscRegFile[misc_reg]);
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return tc->getCpuPtr()->totalInsts() >> 32;
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case MISCREG_CYCLEH:
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DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
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miscRegNames[misc_reg], miscRegFile[misc_reg]);
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return tc->getCpuPtr()->curCycle() >> 32;
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default:
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return readMiscRegNoEffect(misc_reg);
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}
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}
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void
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ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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DPRINTF(RiscvMisc, "Setting CSR %s to 0x%016llx.\n",
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miscRegNames[misc_reg], miscRegNames[misc_reg], val);
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switch (misc_reg) {
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case MISCREG_FFLAGS:
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miscRegFile[MISCREG_FCSR] &= ~0x1F;
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miscRegFile[MISCREG_FCSR] |= bits(val, 4, 0);
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break;
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case MISCREG_FRM:
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miscRegFile[MISCREG_FCSR] &= ~0x70;
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miscRegFile[MISCREG_FCSR] |= bits(val, 2, 0) << 5;
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break;
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case MISCREG_FCSR:
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miscRegFile[MISCREG_FCSR] = bits(val, 7, 0);
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break;
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default:
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miscRegFile[misc_reg] = val;
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break;
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}
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}
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void
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ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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{
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if (bits((unsigned)misc_reg, 11, 10) == 0x3) {
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warn("Ignoring write to read-only CSR.");
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return;
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}
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setMiscRegNoEffect(misc_reg, val);
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}
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}
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RiscvISA::ISA *
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RiscvISAParams::create()
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{
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return new RiscvISA::ISA(this);
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}
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