152 lines
3.8 KiB
C++
152 lines
3.8 KiB
C++
/*
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* Copyright (c) 2016 RISC-V Foundation
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* Copyright (c) 2016 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Alec Roelke
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*/
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#ifndef __ARCH_RISCV_FAULTS_HH__
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#define __ARCH_RISCV_FAULTS_HH__
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#include <string>
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#include "cpu/thread_context.hh"
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#include "sim/faults.hh"
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namespace RiscvISA
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{
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enum ExceptionCode {
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INST_ADDR_MISALIGNED = 0,
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INST_ACCESS = 1,
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INST_ILLEGAL = 2,
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BREAKPOINT = 3,
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LOAD_ADDR_MISALIGNED = 4,
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LOAD_ACCESS = 5,
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STORE_ADDR_MISALIGNED = 6,
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AMO_ADDR_MISALIGNED = 6,
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STORE_ACCESS = 7,
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AMO_ACCESS = 7,
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ECALL_USER = 8,
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ECALL_SUPER = 9,
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ECALL_HYPER = 10,
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ECALL_MACH = 11
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};
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enum InterruptCode {
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SOFTWARE,
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TIMER
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};
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class RiscvFault : public FaultBase
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{
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protected:
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const FaultName _name;
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const ExceptionCode _code;
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const InterruptCode _int;
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RiscvFault(FaultName n, ExceptionCode c, InterruptCode i)
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: _name(n), _code(c), _int(i)
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{}
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FaultName
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name() const
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{
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return _name;
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}
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ExceptionCode
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exception() const
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{
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return _code;
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}
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InterruptCode
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interrupt() const
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{
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return _int;
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}
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virtual void
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invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
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void
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invoke(ThreadContext *tc, const StaticInstPtr &inst);
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};
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class UnknownInstFault : public RiscvFault
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{
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public:
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UnknownInstFault() : RiscvFault("Unknown instruction", INST_ILLEGAL,
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SOFTWARE)
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{}
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void
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invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
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};
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class UnimplementedFault : public RiscvFault
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{
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private:
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const std::string instName;
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public:
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UnimplementedFault(std::string name)
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: RiscvFault("Unimplemented instruction", INST_ILLEGAL, SOFTWARE),
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instName(name)
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{}
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void
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invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
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};
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class BreakpointFault : public RiscvFault
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{
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public:
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BreakpointFault() : RiscvFault("Breakpoint", BREAKPOINT, SOFTWARE)
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{}
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void
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invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
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};
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class SyscallFault : public RiscvFault
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{
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public:
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// TODO: replace ECALL_USER with the appropriate privilege level of the
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// caller
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SyscallFault() : RiscvFault("System call", ECALL_USER, SOFTWARE)
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{}
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void
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invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
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};
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} // namespace RiscvISA
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#endif // __ARCH_RISCV_FAULTS_HH__
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