This website requires JavaScript.
Explore
Help
Sign In
sanchayanmaity
/
gem5
Watch
1
Star
0
Fork
You've already forked gem5
0
Code
Issues
Pull Requests
Packages
Projects
Releases
Wiki
Activity
e76bfc8764
gem5
/
build_opts
/
RISCV
4 lines
76 B
Plaintext
Raw
Blame
History
TARGET_ISA = 'riscv'
CPU_MODELS = 'AtomicSimpleCPU'
PROTOCOL = 'MI_example'
Reference in New Issue
View Git Blame
Copy Permalink