7b07b0877f
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
Change MemReqPtr parameters to references.
--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
339 lines
10 KiB
C++
339 lines
10 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
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#include <string>
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#include <sstream>
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#include <iomanip>
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#include <vector>
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "cpu/memtest/memtest.hh"
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#include "mem/cache/base_cache.hh"
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#include "mem/functional_mem/main_memory.hh"
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#include "sim/builder.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_stats.hh"
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using namespace std;
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MemTest::MemTest(const string &name,
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MemInterface *_cache_interface,
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FunctionalMemory *main_mem,
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FunctionalMemory *check_mem,
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unsigned _memorySize,
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unsigned _percentReads,
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unsigned _percentUncacheable,
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unsigned _progressInterval,
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Addr _traceAddr,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads)
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: BaseCPU(name, 1, 0, 0, max_loads_any_thread, max_loads_all_threads),
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tickEvent(this),
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cacheInterface(_cache_interface),
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mainMem(main_mem),
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checkMem(check_mem),
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size(_memorySize),
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percentReads(_percentReads),
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percentUncacheable(_percentUncacheable),
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progressInterval(_progressInterval),
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nextProgressMessage(_progressInterval)
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{
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vector<string> cmd;
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cmd.push_back("/bin/ls");
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vector<string> null_vec;
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xc = new ExecContext(this ,0,mainMem,0);
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blockSize = cacheInterface->getBlockSize();
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blockAddrMask = blockSize - 1;
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traceBlockAddr = blockAddr(_traceAddr);
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//setup data storage with interesting values
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uint8_t *data1 = new uint8_t[size];
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uint8_t *data2 = new uint8_t[size];
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uint8_t *data3 = new uint8_t[size];
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memset(data1, 1, size);
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memset(data2, 2, size);
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memset(data3, 3, size);
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curTick = 0;
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baseAddr1 = 0x100000;
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baseAddr2 = 0x400000;
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uncacheAddr = 0x800000;
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// set up intial memory contents here
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mainMem->prot_write(baseAddr1, data1, size);
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checkMem->prot_write(baseAddr1, data1, size);
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mainMem->prot_write(baseAddr2, data2, size);
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checkMem->prot_write(baseAddr2, data2, size);
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mainMem->prot_write(uncacheAddr, data3, size);
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checkMem->prot_write(uncacheAddr, data3, size);
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delete [] data1;
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delete [] data2;
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delete [] data3;
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// set up counters
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noResponseCycles = 0;
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numReads = 0;
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numWrites = 0;
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tickEvent.schedule(0);
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}
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static void
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printData(ostream &os, uint8_t *data, int nbytes)
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{
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os << hex << setfill('0');
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// assume little-endian: print bytes from highest address to lowest
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for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
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os << setw(2) << (unsigned)*dp;
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}
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os << dec;
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}
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void
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MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
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{
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switch (req->cmd) {
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case Read:
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if (memcmp(req->data, data, req->size) != 0) {
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cerr << name() << ": on read of 0x" << hex << req->paddr
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<< " @ cycle " << dec << curTick
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<< ", cache returns 0x";
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printData(cerr, req->data, req->size);
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cerr << ", expected 0x";
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printData(cerr, data, req->size);
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cerr << endl;
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fatal("");
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}
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numReads++;
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if (numReads.value() == nextProgressMessage) {
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cerr << name() << ": completed " << numReads.value()
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<< " read accesses @ " << curTick << endl;
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nextProgressMessage += progressInterval;
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}
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comLoadEventQueue[0]->serviceEvents(numReads.value());
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break;
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case Write:
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numWrites++;
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break;
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default:
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panic("invalid command");
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}
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if (blockAddr(req->paddr) == traceBlockAddr) {
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cerr << name() << ": completed "
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<< (req->cmd.isWrite() ? "write" : "read") << " access of "
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<< req->size << " bytes at address 0x"
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<< hex << req->paddr << ", value = 0x";
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printData(cerr, req->data, req->size);
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cerr << " @ cycle " << dec << curTick;
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cerr << endl;
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}
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noResponseCycles = 0;
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delete [] data;
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}
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void
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MemTest::regStats()
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{
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using namespace Statistics;
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numReads
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.name(name() + ".num_reads")
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.desc("number of read accesses completed")
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;
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numWrites
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.name(name() + ".num_writes")
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.desc("number of write accesses completed")
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;
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numCopies
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.name(name() + ".num_copies")
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.desc("number of copy accesses completed")
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;
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}
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void
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MemTest::tick()
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{
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if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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if (++noResponseCycles >= 5000) {
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cerr << name() << ": deadlocked at cycle " << curTick << endl;
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fatal("");
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}
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if (cacheInterface->isBlocked()) {
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return;
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}
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//make new request
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unsigned cmd = rand() % 100;
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unsigned offset1 = random() % size;
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unsigned base = random() % 2;
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uint64_t data = random();
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unsigned access_size = random() % 4;
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unsigned cacheable = rand() % 100;
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MemReqPtr req = new MemReq();
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if (cacheable < percentUncacheable) {
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req->flags |= UNCACHEABLE;
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req->paddr = uncacheAddr + offset1;
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} else {
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req->paddr = ((base) ? baseAddr1 : baseAddr2) + offset1;
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}
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bool probe = (rand() % 2 == 1) && !req->isUncacheable();
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probe = false;
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req->size = 1 << access_size;
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req->data = new uint8_t[req->size];
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req->paddr &= ~(req->size - 1);
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req->time = curTick;
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req->xc = xc;
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if (cmd < percentReads) {
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// read
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req->cmd = Read;
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uint8_t *result = new uint8_t[8];
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checkMem->access(Read, req->paddr, result, req->size);
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if (blockAddr(req->paddr) == traceBlockAddr) {
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cerr << name() << ": initiating read "
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<< ((probe)?"probe of ":"access of ")
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<< req->size << " bytes from addr 0x"
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<< hex << req->paddr << " at cycle "
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<< dec << curTick << endl;
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}
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if (probe) {
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cacheInterface->probeAndUpdate(req);
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completeRequest(req, result);
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} else {
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req->completionEvent = new MemCompleteEvent(req, result, this);
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cacheInterface->access(req);
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}
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} else {
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// write
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req->cmd = Write;
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memcpy(req->data, &data, req->size);
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checkMem->access(Write, req->paddr, req->data, req->size);
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if (blockAddr(req->paddr) == traceBlockAddr) {
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cerr << name() << ": initiating write "
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<< ((probe)?"probe of ":"access of ")
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<< req->size << " bytes (value = 0x";
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printData(cerr, req->data, req->size);
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cerr << ") to addr 0x"
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<< hex << req->paddr << " at cycle "
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<< dec << curTick << endl;
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}
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if (probe) {
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cacheInterface->probeAndUpdate(req);
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completeRequest(req, NULL);
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} else {
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req->completionEvent = new MemCompleteEvent(req, NULL, this);
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cacheInterface->access(req);
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}
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}
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}
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void
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MemCompleteEvent::process()
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{
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tester->completeRequest(req, data);
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delete this;
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}
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const char *
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MemCompleteEvent::description()
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{
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return "memory access completion";
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
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SimObjectParam<BaseCache *> cache;
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SimObjectParam<FunctionalMemory *> main_mem;
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SimObjectParam<FunctionalMemory *> check_mem;
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Param<unsigned> memory_size;
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Param<unsigned> percent_reads;
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Param<unsigned> percent_uncacheable;
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Param<unsigned> progress_interval;
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Param<Addr> trace_addr;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
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BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
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INIT_PARAM(cache, "L1 cache"),
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INIT_PARAM(main_mem, "hierarchical memory"),
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INIT_PARAM(check_mem, "check memory"),
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INIT_PARAM_DFLT(memory_size, "memory size", 65536),
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INIT_PARAM_DFLT(percent_reads, "target read percentage", 65),
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INIT_PARAM_DFLT(percent_uncacheable, "target uncacheable percentage", 10),
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INIT_PARAM_DFLT(progress_interval,
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"progress report interval (in accesses)", 1000000),
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INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
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INIT_PARAM_DFLT(max_loads_any_thread,
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"terminate when any thread reaches this load count",
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0),
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INIT_PARAM_DFLT(max_loads_all_threads,
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"terminate when all threads have reached this load count",
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0)
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END_INIT_SIM_OBJECT_PARAMS(MemTest)
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CREATE_SIM_OBJECT(MemTest)
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{
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return new MemTest(getInstanceName(), cache->getInterface(), main_mem,
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check_mem, memory_size, percent_reads,
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percent_uncacheable, progress_interval,
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trace_addr, max_loads_any_thread,
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max_loads_all_threads);
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}
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REGISTER_SIM_OBJECT("MemTest", MemTest)
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