1504 lines
44 KiB
C++
1504 lines
44 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// Todo:
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// Current ordering allows for 0 cycle added-to-scheduled. Could maybe fake
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// it; either do in reverse order, or have added instructions put into a
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// different ready queue that, in scheduleRreadyInsts(), gets put onto the
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// normal ready queue. This would however give only a one cycle delay,
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// but probably is more flexible to actually add in a delay parameter than
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// just running it backwards.
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#include <limits>
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#include <vector>
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#include "sim/root.hh"
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#include "cpu/o3/fu_pool.hh"
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#include "cpu/o3/inst_queue.hh"
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using namespace std;
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template <class Impl>
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InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
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int fu_idx,
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InstructionQueue<Impl> *iq_ptr)
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: Event(&mainEventQueue, Stat_Event_Pri),
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inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr)
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{
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this->setFlags(Event::AutoDelete);
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}
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template <class Impl>
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void
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InstructionQueue<Impl>::FUCompletion::process()
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{
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iqPtr->processFUCompletion(inst, fuIdx);
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inst = NULL;
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}
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template <class Impl>
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const char *
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InstructionQueue<Impl>::FUCompletion::description()
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{
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return "Functional unit completion event";
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}
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template <class Impl>
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InstructionQueue<Impl>::InstructionQueue(Params *params)
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: dcacheInterface(params->dcacheInterface),
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fuPool(params->fuPool),
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numEntries(params->numIQEntries),
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totalWidth(params->issueWidth),
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numPhysIntRegs(params->numPhysIntRegs),
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numPhysFloatRegs(params->numPhysFloatRegs),
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commitToIEWDelay(params->commitToIEWDelay)
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{
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assert(fuPool);
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numThreads = params->numberOfThreads;
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//Initialize thread IQ counts
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for (int i = 0; i <numThreads; i++) {
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count[i] = 0;
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}
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// Initialize the number of free IQ entries.
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freeEntries = numEntries;
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// Set the number of physical registers as the number of int + float
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numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
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DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
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//Create an entry for each physical register within the
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//dependency graph.
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dependGraph = new DependencyEntry[numPhysRegs];
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// Resize the register scoreboard.
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regScoreboard.resize(numPhysRegs);
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//Initialize Mem Dependence Units
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for (int i = 0; i < numThreads; i++) {
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memDepUnit[i].init(params,i);
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memDepUnit[i].setIQ(this);
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}
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// Initialize all the head pointers to point to NULL, and all the
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// entries as unready.
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// Note that in actuality, the registers corresponding to the logical
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// registers start off as ready. However this doesn't matter for the
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// IQ as the instruction should have been correctly told if those
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// registers are ready in rename. Thus it can all be initialized as
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// unready.
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for (int i = 0; i < numPhysRegs; ++i) {
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dependGraph[i].next = NULL;
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dependGraph[i].inst = NULL;
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regScoreboard[i] = false;
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}
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for (int i = 0; i < numThreads; ++i) {
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squashedSeqNum[i] = 0;
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}
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for (int i = 0; i < Num_OpClasses; ++i) {
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queueOnList[i] = false;
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readyIt[i] = listOrder.end();
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}
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string policy = params->smtIQPolicy;
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//Convert string to lowercase
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std::transform(policy.begin(), policy.end(), policy.begin(),
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(int(*)(int)) tolower);
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//Figure out resource sharing policy
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if (policy == "dynamic") {
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iqPolicy = Dynamic;
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//Set Max Entries to Total ROB Capacity
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for (int i = 0; i < numThreads; i++) {
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maxEntries[i] = numEntries;
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}
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} else if (policy == "partitioned") {
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iqPolicy = Partitioned;
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//@todo:make work if part_amt doesnt divide evenly.
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int part_amt = numEntries / numThreads;
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//Divide ROB up evenly
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for (int i = 0; i < numThreads; i++) {
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maxEntries[i] = part_amt;
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}
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DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
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"%i entries per thread.\n",part_amt);
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} else if (policy == "threshold") {
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iqPolicy = Threshold;
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double threshold = (double)params->smtIQThreshold / 100;
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int thresholdIQ = (int)((double)threshold * numEntries);
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//Divide up by threshold amount
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for (int i = 0; i < numThreads; i++) {
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maxEntries[i] = thresholdIQ;
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}
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DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
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"%i entries per thread.\n",thresholdIQ);
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} else {
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assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
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"Partitioned, Threshold}");
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}
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}
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template <class Impl>
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InstructionQueue<Impl>::~InstructionQueue()
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{
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// Clear the dependency graph
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DependencyEntry *curr;
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DependencyEntry *prev;
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for (int i = 0; i < numPhysRegs; ++i) {
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curr = dependGraph[i].next;
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while (curr) {
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DependencyEntry::mem_alloc_counter--;
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prev = curr;
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curr = prev->next;
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prev->inst = NULL;
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delete prev;
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}
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if (dependGraph[i].inst) {
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dependGraph[i].inst = NULL;
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}
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dependGraph[i].next = NULL;
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}
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assert(DependencyEntry::mem_alloc_counter == 0);
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delete [] dependGraph;
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}
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template <class Impl>
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std::string
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InstructionQueue<Impl>::name() const
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{
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return cpu->name() + ".iq";
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}
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template <class Impl>
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void
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InstructionQueue<Impl>::regStats()
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{
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using namespace Stats;
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iqInstsAdded
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.name(name() + ".iqInstsAdded")
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.desc("Number of instructions added to the IQ (excludes non-spec)")
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.prereq(iqInstsAdded);
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iqNonSpecInstsAdded
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.name(name() + ".iqNonSpecInstsAdded")
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.desc("Number of non-speculative instructions added to the IQ")
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.prereq(iqNonSpecInstsAdded);
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// iqIntInstsAdded;
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iqInstsIssued
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.name(name() + ".iqInstsIssued")
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.desc("Number of instructions issued")
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.prereq(iqInstsIssued);
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iqIntInstsIssued
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.name(name() + ".iqIntInstsIssued")
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.desc("Number of integer instructions issued")
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.prereq(iqIntInstsIssued);
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// iqFloatInstsAdded;
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iqFloatInstsIssued
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.name(name() + ".iqFloatInstsIssued")
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.desc("Number of float instructions issued")
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.prereq(iqFloatInstsIssued);
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// iqBranchInstsAdded;
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iqBranchInstsIssued
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.name(name() + ".iqBranchInstsIssued")
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.desc("Number of branch instructions issued")
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.prereq(iqBranchInstsIssued);
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// iqMemInstsAdded;
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iqMemInstsIssued
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.name(name() + ".iqMemInstsIssued")
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.desc("Number of memory instructions issued")
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.prereq(iqMemInstsIssued);
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// iqMiscInstsAdded;
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iqMiscInstsIssued
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.name(name() + ".iqMiscInstsIssued")
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.desc("Number of miscellaneous instructions issued")
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.prereq(iqMiscInstsIssued);
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iqSquashedInstsIssued
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.name(name() + ".iqSquashedInstsIssued")
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.desc("Number of squashed instructions issued")
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.prereq(iqSquashedInstsIssued);
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iqSquashedInstsExamined
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.name(name() + ".iqSquashedInstsExamined")
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.desc("Number of squashed instructions iterated over during squash;"
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" mainly for profiling")
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.prereq(iqSquashedInstsExamined);
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iqSquashedOperandsExamined
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.name(name() + ".iqSquashedOperandsExamined")
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.desc("Number of squashed operands that are examined and possibly "
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"removed from graph")
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.prereq(iqSquashedOperandsExamined);
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iqSquashedNonSpecRemoved
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.name(name() + ".iqSquashedNonSpecRemoved")
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.desc("Number of squashed non-spec instructions that were removed")
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.prereq(iqSquashedNonSpecRemoved);
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queue_res_dist
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.init(Num_OpClasses, 0, 99, 2)
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.name(name() + ".IQ:residence:")
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.desc("cycles from dispatch to issue")
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.flags(total | pdf | cdf )
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;
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for (int i = 0; i < Num_OpClasses; ++i) {
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queue_res_dist.subname(i, opClassStrings[i]);
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}
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n_issued_dist
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.init(totalWidth + 1)
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.name(name() + ".ISSUE:issued_per_cycle")
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.desc("Number of insts issued each cycle")
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.flags(total | pdf | dist)
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;
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/*
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dist_unissued
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.init(Num_OpClasses+2)
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.name(name() + ".ISSUE:unissued_cause")
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.desc("Reason ready instruction not issued")
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.flags(pdf | dist)
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;
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for (int i=0; i < (Num_OpClasses + 2); ++i) {
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dist_unissued.subname(i, unissued_names[i]);
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}
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*/
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stat_issued_inst_type
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.init(numThreads,Num_OpClasses)
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.name(name() + ".ISSUE:FU_type")
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.desc("Type of FU issued")
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.flags(total | pdf | dist)
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;
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stat_issued_inst_type.ysubnames(opClassStrings);
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//
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// How long did instructions for a particular FU type wait prior to issue
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//
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issue_delay_dist
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.init(Num_OpClasses,0,99,2)
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.name(name() + ".ISSUE:")
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.desc("cycles from operands ready to issue")
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.flags(pdf | cdf)
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;
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for (int i=0; i<Num_OpClasses; ++i) {
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stringstream subname;
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subname << opClassStrings[i] << "_delay";
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issue_delay_dist.subname(i, subname.str());
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}
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issue_rate
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.name(name() + ".ISSUE:rate")
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.desc("Inst issue rate")
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.flags(total)
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;
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issue_rate = iqInstsIssued / cpu->numCycles;
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/*
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issue_stores
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.name(name() + ".ISSUE:stores")
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.desc("Number of stores issued")
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.flags(total)
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;
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issue_stores = exe_refs - exe_loads;
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*/
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/*
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issue_op_rate
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.name(name() + ".ISSUE:op_rate")
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.desc("Operation issue rate")
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.flags(total)
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;
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issue_op_rate = issued_ops / numCycles;
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*/
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stat_fu_busy
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.init(Num_OpClasses)
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.name(name() + ".ISSUE:fu_full")
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.desc("attempts to use FU when none available")
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.flags(pdf | dist)
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;
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for (int i=0; i < Num_OpClasses; ++i) {
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stat_fu_busy.subname(i, opClassStrings[i]);
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}
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fu_busy
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.init(numThreads)
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.name(name() + ".ISSUE:fu_busy_cnt")
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.desc("FU busy when requested")
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.flags(total)
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;
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fu_busy_rate
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.name(name() + ".ISSUE:fu_busy_rate")
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.desc("FU busy rate (busy events/executed inst)")
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.flags(total)
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;
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fu_busy_rate = fu_busy / iqInstsIssued;
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for ( int i=0; i < numThreads; i++) {
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// Tell mem dependence unit to reg stats as well.
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memDepUnit[i].regStats();
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}
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}
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template <class Impl>
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void
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InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
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{
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DPRINTF(IQ, "Setting active threads list pointer.\n");
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activeThreads = at_ptr;
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}
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template <class Impl>
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void
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InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
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{
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DPRINTF(IQ, "Set the issue to execute queue.\n");
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issueToExecuteQueue = i2e_ptr;
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}
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template <class Impl>
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void
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InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
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{
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DPRINTF(IQ, "Set the time buffer.\n");
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timeBuffer = tb_ptr;
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fromCommit = timeBuffer->getWire(-commitToIEWDelay);
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}
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template <class Impl>
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int
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InstructionQueue<Impl>::entryAmount(int num_threads)
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{
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if (iqPolicy == Partitioned) {
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return numEntries / num_threads;
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} else {
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return 0;
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}
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}
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template <class Impl>
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void
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InstructionQueue<Impl>::resetEntries()
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{
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if (iqPolicy != Dynamic || numThreads > 1) {
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int active_threads = (*activeThreads).size();
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list<unsigned>::iterator threads = (*activeThreads).begin();
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list<unsigned>::iterator list_end = (*activeThreads).end();
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while (threads != list_end) {
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if (iqPolicy == Partitioned) {
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maxEntries[*threads++] = numEntries / active_threads;
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} else if(iqPolicy == Threshold && active_threads == 1) {
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maxEntries[*threads++] = numEntries;
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}
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}
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}
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}
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template <class Impl>
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unsigned
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InstructionQueue<Impl>::numFreeEntries()
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{
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return freeEntries;
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}
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template <class Impl>
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unsigned
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InstructionQueue<Impl>::numFreeEntries(unsigned tid)
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{
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return maxEntries[tid] - count[tid];
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}
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// Might want to do something more complex if it knows how many instructions
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// will be issued this cycle.
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template <class Impl>
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bool
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InstructionQueue<Impl>::isFull()
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{
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if (freeEntries == 0) {
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return(true);
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} else {
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return(false);
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}
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}
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template <class Impl>
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bool
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InstructionQueue<Impl>::isFull(unsigned tid)
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{
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if (numFreeEntries(tid) == 0) {
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return(true);
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} else {
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return(false);
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}
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}
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template <class Impl>
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bool
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InstructionQueue<Impl>::hasReadyInsts()
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{
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if (!listOrder.empty()) {
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return true;
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}
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for (int i = 0; i < Num_OpClasses; ++i) {
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if (!readyInsts[i].empty()) {
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return true;
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}
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}
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return false;
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}
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template <class Impl>
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void
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InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
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{
|
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// Make sure the instruction is valid
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assert(new_inst);
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DPRINTF(IQ, "Adding instruction PC %#x to the IQ.\n",
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new_inst->readPC());
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// Check if there are any free entries. Panic if there are none.
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// Might want to have this return a fault in the future instead of
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// panicing.
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assert(freeEntries != 0);
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instList[new_inst->threadNumber].push_back(new_inst);
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// Decrease the number of free entries.
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--freeEntries;
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//Mark Instruction as in IQ
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new_inst->setInIQ();
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// Look through its source registers (physical regs), and mark any
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// dependencies.
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addToDependents(new_inst);
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// Have this instruction set itself as the producer of its destination
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// register(s).
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createDependency(new_inst);
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// If it's a memory instruction, add it to the memory dependency
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// unit.
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if (new_inst->isMemRef()) {
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memDepUnit[new_inst->threadNumber].insert(new_inst);
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} else {
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// If the instruction is ready then add it to the ready list.
|
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addIfReady(new_inst);
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}
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++iqInstsAdded;
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//Update Thread IQ Count
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count[new_inst->threadNumber]++;
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|
|
|
assert(freeEntries == (numEntries - countInsts()));
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
|
|
{
|
|
// @todo: Clean up this code; can do it by setting inst as unable
|
|
// to issue, then calling normal insert on the inst.
|
|
|
|
// Make sure the instruction is valid
|
|
assert(new_inst);
|
|
|
|
nonSpecInsts[new_inst->seqNum] = new_inst;
|
|
|
|
DPRINTF(IQ, "Adding instruction PC %#x to the IQ.\n",
|
|
new_inst->readPC());
|
|
|
|
// Check if there are any free entries. Panic if there are none.
|
|
// Might want to have this return a fault in the future instead of
|
|
// panicing.
|
|
assert(freeEntries != 0);
|
|
|
|
instList[new_inst->threadNumber].push_back(new_inst);
|
|
|
|
// Decrease the number of free entries.
|
|
--freeEntries;
|
|
|
|
//Mark Instruction as in IQ
|
|
new_inst->setInIQ();
|
|
|
|
// Have this instruction set itself as the producer of its destination
|
|
// register(s).
|
|
createDependency(new_inst);
|
|
|
|
// If it's a memory instruction, add it to the memory dependency
|
|
// unit.
|
|
if (new_inst->isMemRef()) {
|
|
memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
|
|
}
|
|
|
|
++iqNonSpecInstsAdded;
|
|
|
|
//Update Thread IQ Count
|
|
count[new_inst->threadNumber]++;
|
|
|
|
assert(freeEntries == (numEntries - countInsts()));
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
|
|
{
|
|
memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
|
|
|
|
insertNonSpec(barr_inst);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::advanceTail(DynInstPtr &inst)
|
|
{
|
|
// Have this instruction set itself as the producer of its destination
|
|
// register(s).
|
|
createDependency(inst);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::addToOrderList(OpClass op_class)
|
|
{
|
|
assert(!readyInsts[op_class].empty());
|
|
|
|
ListOrderEntry queue_entry;
|
|
|
|
queue_entry.queueType = op_class;
|
|
|
|
queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
|
|
|
|
ListOrderIt list_it = listOrder.begin();
|
|
ListOrderIt list_end_it = listOrder.end();
|
|
|
|
while (list_it != list_end_it) {
|
|
if ((*list_it).oldestInst > queue_entry.oldestInst) {
|
|
break;
|
|
}
|
|
|
|
list_it++;
|
|
}
|
|
|
|
readyIt[op_class] = listOrder.insert(list_it, queue_entry);
|
|
queueOnList[op_class] = true;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
|
|
{
|
|
// Get iterator of next item on the list
|
|
// Delete the original iterator
|
|
// Determine if the next item is either the end of the list or younger
|
|
// than the new instruction. If so, then add in a new iterator right here.
|
|
// If not, then move along.
|
|
ListOrderEntry queue_entry;
|
|
OpClass op_class = (*list_order_it).queueType;
|
|
ListOrderIt next_it = list_order_it;
|
|
|
|
++next_it;
|
|
|
|
queue_entry.queueType = op_class;
|
|
queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
|
|
|
|
while (next_it != listOrder.end() &&
|
|
(*next_it).oldestInst < queue_entry.oldestInst) {
|
|
++next_it;
|
|
}
|
|
|
|
readyIt[op_class] = listOrder.insert(next_it, queue_entry);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
|
|
{
|
|
// The CPU could have been sleeping until this op completed (*extremely*
|
|
// long latency op). Wake it if it was. This may be overkill.
|
|
iewStage->wakeCPU();
|
|
|
|
fuPool->freeUnit(fu_idx);
|
|
|
|
int &size = issueToExecuteQueue->access(0)->size;
|
|
|
|
issueToExecuteQueue->access(0)->insts[size++] = inst;
|
|
}
|
|
|
|
// @todo: Figure out a better way to remove the squashed items from the
|
|
// lists. Checking the top item of each list to see if it's squashed
|
|
// wastes time and forces jumps.
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::scheduleReadyInsts()
|
|
{
|
|
DPRINTF(IQ, "Attempting to schedule ready instructions from "
|
|
"the IQ.\n");
|
|
|
|
IssueStruct *i2e_info = issueToExecuteQueue->access(0);
|
|
|
|
// Will need to reorder the list if either a queue is not on the list,
|
|
// or it has an older instruction than last time.
|
|
for (int i = 0; i < Num_OpClasses; ++i) {
|
|
if (!readyInsts[i].empty()) {
|
|
if (!queueOnList[i]) {
|
|
addToOrderList(OpClass(i));
|
|
} else if (readyInsts[i].top()->seqNum <
|
|
(*readyIt[i]).oldestInst) {
|
|
listOrder.erase(readyIt[i]);
|
|
addToOrderList(OpClass(i));
|
|
}
|
|
}
|
|
}
|
|
|
|
// Have iterator to head of the list
|
|
// While I haven't exceeded bandwidth or reached the end of the list,
|
|
// Try to get a FU that can do what this op needs.
|
|
// If successful, change the oldestInst to the new top of the list, put
|
|
// the queue in the proper place in the list.
|
|
// Increment the iterator.
|
|
// This will avoid trying to schedule a certain op class if there are no
|
|
// FUs that handle it.
|
|
ListOrderIt order_it = listOrder.begin();
|
|
ListOrderIt order_end_it = listOrder.end();
|
|
int total_issued = 0;
|
|
int exec_queue_slot = i2e_info->size;
|
|
|
|
while (exec_queue_slot < totalWidth && order_it != order_end_it) {
|
|
OpClass op_class = (*order_it).queueType;
|
|
|
|
assert(!readyInsts[op_class].empty());
|
|
|
|
DynInstPtr issuing_inst = readyInsts[op_class].top();
|
|
|
|
assert(issuing_inst->seqNum == (*order_it).oldestInst);
|
|
|
|
if (issuing_inst->isSquashed()) {
|
|
readyInsts[op_class].pop();
|
|
|
|
if (!readyInsts[op_class].empty()) {
|
|
moveToYoungerInst(order_it);
|
|
} else {
|
|
readyIt[op_class] = listOrder.end();
|
|
queueOnList[op_class] = false;
|
|
}
|
|
|
|
listOrder.erase(order_it++);
|
|
|
|
++iqSquashedInstsIssued;
|
|
|
|
continue;
|
|
}
|
|
|
|
int idx = fuPool->getUnit(op_class);
|
|
|
|
int tid = issuing_inst->threadNumber;
|
|
|
|
if (idx == -2) {
|
|
assert(op_class == No_OpClass);
|
|
|
|
i2e_info->insts[exec_queue_slot++] = issuing_inst;
|
|
i2e_info->size++;
|
|
|
|
DPRINTF(IQ, "Thread %i: Issuing instruction PC that needs no FU"
|
|
" %#x [sn:%lli]\n",
|
|
tid, issuing_inst->readPC(),
|
|
issuing_inst->seqNum);
|
|
|
|
readyInsts[op_class].pop();
|
|
|
|
if (!readyInsts[op_class].empty()) {
|
|
moveToYoungerInst(order_it);
|
|
} else {
|
|
readyIt[op_class] = listOrder.end();
|
|
queueOnList[op_class] = false;
|
|
}
|
|
|
|
issuing_inst->setIssued();
|
|
++total_issued;
|
|
|
|
if (!issuing_inst->isMemRef()) {
|
|
// Memory instructions can not be freed from the IQ until they
|
|
// complete.
|
|
++freeEntries;
|
|
count[tid]--;
|
|
issuing_inst->removeInIQ();
|
|
} else {
|
|
memDepUnit[tid].issue(issuing_inst);
|
|
}
|
|
|
|
listOrder.erase(order_it++);
|
|
|
|
stat_issued_inst_type[tid][op_class]++;
|
|
} else if (idx != -1) {
|
|
int op_latency = fuPool->getOpLatency(op_class);
|
|
|
|
if (op_latency == 1) {
|
|
i2e_info->insts[exec_queue_slot++] = issuing_inst;
|
|
i2e_info->size++;
|
|
|
|
// Add the FU onto the list of FU's to be freed next cycle.
|
|
fuPool->freeUnit(idx);
|
|
} else {
|
|
int issue_latency = fuPool->getIssueLatency(op_class);
|
|
|
|
if (issue_latency > 1) {
|
|
// Generate completion event for the FU
|
|
FUCompletion *execution = new FUCompletion(issuing_inst,
|
|
idx, this);
|
|
|
|
execution->schedule(curTick + issue_latency - 1);
|
|
} else {
|
|
i2e_info->insts[exec_queue_slot++] = issuing_inst;
|
|
i2e_info->size++;
|
|
|
|
// Add the FU onto the list of FU's to be freed next cycle.
|
|
fuPool->freeUnit(idx);
|
|
}
|
|
}
|
|
|
|
DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
|
|
"[sn:%lli]\n",
|
|
tid, issuing_inst->readPC(),
|
|
issuing_inst->seqNum);
|
|
|
|
readyInsts[op_class].pop();
|
|
|
|
if (!readyInsts[op_class].empty()) {
|
|
moveToYoungerInst(order_it);
|
|
} else {
|
|
readyIt[op_class] = listOrder.end();
|
|
queueOnList[op_class] = false;
|
|
}
|
|
|
|
issuing_inst->setIssued();
|
|
++total_issued;
|
|
|
|
if (!issuing_inst->isMemRef()) {
|
|
// Memory instructions can not be freed from the IQ until they
|
|
// complete.
|
|
++freeEntries;
|
|
count[tid]--;
|
|
issuing_inst->removeInIQ();
|
|
} else {
|
|
memDepUnit[tid].issue(issuing_inst);
|
|
}
|
|
|
|
listOrder.erase(order_it++);
|
|
stat_issued_inst_type[tid][op_class]++;
|
|
} else {
|
|
stat_fu_busy[op_class]++;
|
|
fu_busy[tid]++;
|
|
++order_it;
|
|
}
|
|
}
|
|
|
|
if (total_issued) {
|
|
cpu->activityThisCycle();
|
|
} else {
|
|
DPRINTF(IQ, "Not able to schedule any instructions.\n");
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
|
|
{
|
|
DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
|
|
"to execute.\n", inst);
|
|
|
|
NonSpecMapIt inst_it = nonSpecInsts.find(inst);
|
|
|
|
assert(inst_it != nonSpecInsts.end());
|
|
|
|
unsigned tid = (*inst_it).second->threadNumber;
|
|
|
|
// Mark this instruction as ready to issue.
|
|
(*inst_it).second->setCanIssue();
|
|
|
|
// Now schedule the instruction.
|
|
if (!(*inst_it).second->isMemRef()) {
|
|
addIfReady((*inst_it).second);
|
|
} else {
|
|
memDepUnit[tid].nonSpecInstReady((*inst_it).second);
|
|
}
|
|
|
|
(*inst_it).second = NULL;
|
|
|
|
nonSpecInsts.erase(inst_it);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
|
|
{
|
|
/*Need to go through each thread??*/
|
|
DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
|
|
tid,inst);
|
|
|
|
ListIt iq_it = instList[tid].begin();
|
|
|
|
while (iq_it != instList[tid].end() &&
|
|
(*iq_it)->seqNum <= inst) {
|
|
++iq_it;
|
|
instList[tid].pop_front();
|
|
}
|
|
|
|
assert(freeEntries == (numEntries - countInsts()));
|
|
}
|
|
|
|
template <class Impl>
|
|
int
|
|
InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
|
|
{
|
|
int dependents = 0;
|
|
|
|
DPRINTF(IQ, "Waking dependents of completed instruction.\n");
|
|
|
|
assert(!completed_inst->isSquashed());
|
|
// Look at the physical destination register of the DynInst
|
|
// and look it up on the dependency graph. Then mark as ready
|
|
// any instructions within the instruction queue.
|
|
DependencyEntry *curr;
|
|
DependencyEntry *prev;
|
|
|
|
// Tell the memory dependence unit to wake any dependents on this
|
|
// instruction if it is a memory instruction. Also complete the memory
|
|
// instruction at this point since we know it executed fine.
|
|
// @todo: Might want to rename "completeMemInst" to
|
|
// something that indicates that it won't need to be replayed, and call
|
|
// this earlier. Might not be a big deal.
|
|
if (completed_inst->isMemRef()) {
|
|
memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
|
|
completeMemInst(completed_inst);
|
|
} else if (completed_inst->isMemBarrier() ||
|
|
completed_inst->isWriteBarrier()) {
|
|
memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
|
|
}
|
|
|
|
for (int dest_reg_idx = 0;
|
|
dest_reg_idx < completed_inst->numDestRegs();
|
|
dest_reg_idx++)
|
|
{
|
|
PhysRegIndex dest_reg =
|
|
completed_inst->renamedDestRegIdx(dest_reg_idx);
|
|
|
|
// Special case of uniq or control registers. They are not
|
|
// handled by the IQ and thus have no dependency graph entry.
|
|
// @todo Figure out a cleaner way to handle this.
|
|
if (dest_reg >= numPhysRegs) {
|
|
continue;
|
|
}
|
|
|
|
DPRINTF(IQ, "Waking any dependents on register %i.\n",
|
|
(int) dest_reg);
|
|
|
|
//Maybe abstract this part into a function.
|
|
//Go through the dependency chain, marking the registers as ready
|
|
//within the waiting instructions.
|
|
|
|
curr = dependGraph[dest_reg].next;
|
|
|
|
while (curr) {
|
|
DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
|
|
curr->inst->readPC());
|
|
|
|
// Might want to give more information to the instruction
|
|
// so that it knows which of its source registers is ready.
|
|
// However that would mean that the dependency graph entries
|
|
// would need to hold the src_reg_idx.
|
|
curr->inst->markSrcRegReady();
|
|
|
|
addIfReady(curr->inst);
|
|
|
|
DependencyEntry::mem_alloc_counter--;
|
|
|
|
prev = curr;
|
|
curr = prev->next;
|
|
prev->inst = NULL;
|
|
|
|
++dependents;
|
|
|
|
delete prev;
|
|
}
|
|
|
|
// Reset the head node now that all of its dependents have been woken
|
|
// up.
|
|
dependGraph[dest_reg].next = NULL;
|
|
dependGraph[dest_reg].inst = NULL;
|
|
|
|
// Mark the scoreboard as having that register ready.
|
|
regScoreboard[dest_reg] = true;
|
|
}
|
|
return dependents;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
|
|
{
|
|
OpClass op_class = ready_inst->opClass();
|
|
|
|
readyInsts[op_class].push(ready_inst);
|
|
|
|
DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
|
|
"the ready list, PC %#x opclass:%i [sn:%lli].\n",
|
|
ready_inst->readPC(), op_class, ready_inst->seqNum);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
|
|
{
|
|
memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
|
|
{
|
|
memDepUnit[replay_inst->threadNumber].replay(replay_inst);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
|
|
{
|
|
int tid = completed_inst->threadNumber;
|
|
|
|
DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
|
|
completed_inst->readPC(), completed_inst->seqNum);
|
|
|
|
++freeEntries;
|
|
|
|
completed_inst->memOpDone = true;
|
|
|
|
memDepUnit[tid].completed(completed_inst);
|
|
|
|
count[tid]--;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::violation(DynInstPtr &store,
|
|
DynInstPtr &faulting_load)
|
|
{
|
|
memDepUnit[store->threadNumber].violation(store, faulting_load);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::squash(unsigned tid)
|
|
{
|
|
DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
|
|
"the IQ.\n", tid);
|
|
|
|
// Read instruction sequence number of last instruction out of the
|
|
// time buffer.
|
|
squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
|
|
|
|
// Setup the squash iterator to point to the tail.
|
|
squashIt[tid] = instList[tid].end();
|
|
--squashIt[tid];
|
|
|
|
// Call doSquash if there are insts in the IQ
|
|
if (count[tid] > 0) {
|
|
doSquash(tid);
|
|
}
|
|
|
|
// Also tell the memory dependence unit to squash.
|
|
memDepUnit[tid].squash(squashedSeqNum[tid], tid);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::doSquash(unsigned tid)
|
|
{
|
|
// Make sure the squashed sequence number is valid.
|
|
// assert(squashedSeqNum[tid] != 0);
|
|
|
|
DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
|
|
tid, squashedSeqNum[tid]);
|
|
|
|
// Squash any instructions younger than the squashed sequence number
|
|
// given.
|
|
while (squashIt[tid] != instList[tid].end() &&
|
|
(*squashIt[tid])->seqNum > squashedSeqNum[tid]) {
|
|
|
|
DynInstPtr squashed_inst = (*squashIt[tid]);
|
|
|
|
// Only handle the instruction if it actually is in the IQ and
|
|
// hasn't already been squashed in the IQ.
|
|
if (squashed_inst->threadNumber != tid ||
|
|
squashed_inst->isSquashedInIQ()) {
|
|
--squashIt[tid];
|
|
continue;
|
|
}
|
|
|
|
if (!squashed_inst->isIssued() ||
|
|
(squashed_inst->isMemRef() &&
|
|
!squashed_inst->memOpDone)) {
|
|
|
|
// Remove the instruction from the dependency list.
|
|
if (!squashed_inst->isNonSpeculative() &&
|
|
!squashed_inst->isMemBarrier() &&
|
|
!squashed_inst->isWriteBarrier()) {
|
|
|
|
for (int src_reg_idx = 0;
|
|
src_reg_idx < squashed_inst->numSrcRegs();
|
|
src_reg_idx++)
|
|
{
|
|
PhysRegIndex src_reg =
|
|
squashed_inst->renamedSrcRegIdx(src_reg_idx);
|
|
|
|
// Only remove it from the dependency graph if it was
|
|
// placed there in the first place.
|
|
// HACK: This assumes that instructions woken up from the
|
|
// dependency chain aren't informed that a specific src
|
|
// register has become ready. This may not always be true
|
|
// in the future.
|
|
// Instead of doing a linked list traversal, we can just
|
|
// remove these squashed instructions either at issue time,
|
|
// or when the register is overwritten. The only downside
|
|
// to this is it leaves more room for error.
|
|
|
|
if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
|
|
src_reg < numPhysRegs) {
|
|
dependGraph[src_reg].remove(squashed_inst);
|
|
}
|
|
|
|
|
|
++iqSquashedOperandsExamined;
|
|
}
|
|
|
|
// Might want to remove producers as well.
|
|
} else {
|
|
NonSpecMapIt ns_inst_it =
|
|
nonSpecInsts.find(squashed_inst->seqNum);
|
|
assert(ns_inst_it != nonSpecInsts.end());
|
|
|
|
(*ns_inst_it).second = NULL;
|
|
|
|
nonSpecInsts.erase(ns_inst_it);
|
|
|
|
++iqSquashedNonSpecRemoved;
|
|
}
|
|
|
|
// Might want to also clear out the head of the dependency graph.
|
|
|
|
// Mark it as squashed within the IQ.
|
|
squashed_inst->setSquashedInIQ();
|
|
|
|
// @todo: Remove this hack where several statuses are set so the
|
|
// inst will flow through the rest of the pipeline.
|
|
squashed_inst->setIssued();
|
|
squashed_inst->setCanCommit();
|
|
squashed_inst->removeInIQ();
|
|
|
|
//Update Thread IQ Count
|
|
count[squashed_inst->threadNumber]--;
|
|
|
|
++freeEntries;
|
|
|
|
if (numThreads > 1) {
|
|
DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
|
|
"squashed.\n",
|
|
tid, squashed_inst->seqNum, squashed_inst->readPC());
|
|
} else {
|
|
DPRINTF(IQ, "Instruction [sn:%lli] PC %#x squashed.\n",
|
|
squashed_inst->seqNum, squashed_inst->readPC());
|
|
}
|
|
}
|
|
|
|
instList[tid].erase(squashIt[tid]--);
|
|
++iqSquashedInstsExamined;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::DependencyEntry::insert(DynInstPtr &new_inst)
|
|
{
|
|
//Add this new, dependent instruction at the head of the dependency
|
|
//chain.
|
|
|
|
// First create the entry that will be added to the head of the
|
|
// dependency chain.
|
|
DependencyEntry *new_entry = new DependencyEntry;
|
|
new_entry->next = this->next;
|
|
new_entry->inst = new_inst;
|
|
|
|
// Then actually add it to the chain.
|
|
this->next = new_entry;
|
|
|
|
++mem_alloc_counter;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::DependencyEntry::remove(DynInstPtr &inst_to_remove)
|
|
{
|
|
DependencyEntry *prev = this;
|
|
DependencyEntry *curr = this->next;
|
|
|
|
// Make sure curr isn't NULL. Because this instruction is being
|
|
// removed from a dependency list, it must have been placed there at
|
|
// an earlier time. The dependency chain should not be empty,
|
|
// unless the instruction dependent upon it is already ready.
|
|
if (curr == NULL) {
|
|
return;
|
|
}
|
|
|
|
// Find the instruction to remove within the dependency linked list.
|
|
while (curr->inst != inst_to_remove) {
|
|
prev = curr;
|
|
curr = curr->next;
|
|
|
|
assert(curr != NULL);
|
|
}
|
|
|
|
// Now remove this instruction from the list.
|
|
prev->next = curr->next;
|
|
|
|
--mem_alloc_counter;
|
|
|
|
// Could push this off to the destructor of DependencyEntry
|
|
curr->inst = NULL;
|
|
|
|
delete curr;
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
|
|
{
|
|
// Loop through the instruction's source registers, adding
|
|
// them to the dependency list if they are not ready.
|
|
int8_t total_src_regs = new_inst->numSrcRegs();
|
|
bool return_val = false;
|
|
|
|
for (int src_reg_idx = 0;
|
|
src_reg_idx < total_src_regs;
|
|
src_reg_idx++)
|
|
{
|
|
// Only add it to the dependency graph if it's not ready.
|
|
if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
|
|
PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
|
|
|
|
// Check the IQ's scoreboard to make sure the register
|
|
// hasn't become ready while the instruction was in flight
|
|
// between stages. Only if it really isn't ready should
|
|
// it be added to the dependency graph.
|
|
if (src_reg >= numPhysRegs) {
|
|
continue;
|
|
} else if (regScoreboard[src_reg] == false) {
|
|
DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
|
|
"is being added to the dependency chain.\n",
|
|
new_inst->readPC(), src_reg);
|
|
|
|
dependGraph[src_reg].insert(new_inst);
|
|
|
|
// Change the return value to indicate that something
|
|
// was added to the dependency graph.
|
|
return_val = true;
|
|
} else {
|
|
DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
|
|
"became ready before it reached the IQ.\n",
|
|
new_inst->readPC(), src_reg);
|
|
// Mark a register ready within the instruction.
|
|
new_inst->markSrcRegReady();
|
|
}
|
|
}
|
|
}
|
|
|
|
return return_val;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::createDependency(DynInstPtr &new_inst)
|
|
{
|
|
//Actually nothing really needs to be marked when an
|
|
//instruction becomes the producer of a register's value,
|
|
//but for convenience a ptr to the producing instruction will
|
|
//be placed in the head node of the dependency links.
|
|
int8_t total_dest_regs = new_inst->numDestRegs();
|
|
|
|
for (int dest_reg_idx = 0;
|
|
dest_reg_idx < total_dest_regs;
|
|
dest_reg_idx++)
|
|
{
|
|
PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
|
|
|
|
// Instructions that use the misc regs will have a reg number
|
|
// higher than the normal physical registers. In this case these
|
|
// registers are not renamed, and there is no need to track
|
|
// dependencies as these instructions must be executed at commit.
|
|
if (dest_reg >= numPhysRegs) {
|
|
continue;
|
|
}
|
|
|
|
if (dependGraph[dest_reg].next) {
|
|
dumpDependGraph();
|
|
panic("Dependency graph %i not empty!", dest_reg);
|
|
}
|
|
|
|
dependGraph[dest_reg].inst = new_inst;
|
|
|
|
// Mark the scoreboard to say it's not yet ready.
|
|
regScoreboard[dest_reg] = false;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
|
|
{
|
|
//If the instruction now has all of its source registers
|
|
// available, then add it to the list of ready instructions.
|
|
if (inst->readyToIssue()) {
|
|
|
|
//Add the instruction to the proper ready list.
|
|
if (inst->isMemRef()) {
|
|
|
|
DPRINTF(IQ, "Checking if memory instruction can issue.\n");
|
|
|
|
// Message to the mem dependence unit that this instruction has
|
|
// its registers ready.
|
|
|
|
memDepUnit[inst->threadNumber].regsReady(inst);
|
|
|
|
return;
|
|
}
|
|
|
|
OpClass op_class = inst->opClass();
|
|
|
|
DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
|
|
"the ready list, PC %#x opclass:%i [sn:%lli].\n",
|
|
inst->readPC(), op_class, inst->seqNum);
|
|
|
|
readyInsts[op_class].push(inst);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
int
|
|
InstructionQueue<Impl>::countInsts()
|
|
{
|
|
//ksewell:This works but definitely could use a cleaner write
|
|
//with a more intuitive way of counting. Right now it's
|
|
//just brute force ....
|
|
|
|
#if 0
|
|
int total_insts = 0;
|
|
|
|
for (int i = 0; i < numThreads; ++i) {
|
|
ListIt count_it = instList[i].begin();
|
|
|
|
while (count_it != instList[i].end()) {
|
|
if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
|
|
if (!(*count_it)->isIssued()) {
|
|
++total_insts;
|
|
} else if ((*count_it)->isMemRef() &&
|
|
!(*count_it)->memOpDone) {
|
|
// Loads that have not been marked as executed still count
|
|
// towards the total instructions.
|
|
++total_insts;
|
|
}
|
|
}
|
|
|
|
++count_it;
|
|
}
|
|
}
|
|
|
|
return total_insts;
|
|
#else
|
|
return numEntries - freeEntries;
|
|
#endif
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::dumpDependGraph()
|
|
{
|
|
DependencyEntry *curr;
|
|
|
|
for (int i = 0; i < numPhysRegs; ++i)
|
|
{
|
|
curr = &dependGraph[i];
|
|
|
|
if (curr->inst) {
|
|
cprintf("dependGraph[%i]: producer: %#x [sn:%lli] consumer: ",
|
|
i, curr->inst->readPC(), curr->inst->seqNum);
|
|
} else {
|
|
cprintf("dependGraph[%i]: No producer. consumer: ", i);
|
|
}
|
|
|
|
while (curr->next != NULL) {
|
|
curr = curr->next;
|
|
|
|
cprintf("%#x [sn:%lli] ",
|
|
curr->inst->readPC(), curr->inst->seqNum);
|
|
}
|
|
|
|
cprintf("\n");
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::dumpLists()
|
|
{
|
|
for (int i = 0; i < Num_OpClasses; ++i) {
|
|
cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
|
|
|
|
cprintf("\n");
|
|
}
|
|
|
|
cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
|
|
|
|
NonSpecMapIt non_spec_it = nonSpecInsts.begin();
|
|
NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
|
|
|
|
cprintf("Non speculative list: ");
|
|
|
|
while (non_spec_it != non_spec_end_it) {
|
|
cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
|
|
(*non_spec_it).second->seqNum);
|
|
++non_spec_it;
|
|
}
|
|
|
|
cprintf("\n");
|
|
|
|
ListOrderIt list_order_it = listOrder.begin();
|
|
ListOrderIt list_order_end_it = listOrder.end();
|
|
int i = 1;
|
|
|
|
cprintf("List order: ");
|
|
|
|
while (list_order_it != list_order_end_it) {
|
|
cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
|
|
(*list_order_it).oldestInst);
|
|
|
|
++list_order_it;
|
|
++i;
|
|
}
|
|
|
|
cprintf("\n");
|
|
}
|
|
|
|
|
|
template <class Impl>
|
|
void
|
|
InstructionQueue<Impl>::dumpInsts()
|
|
{
|
|
for (int i = 0; i < numThreads; ++i) {
|
|
int num = 0;
|
|
int valid_num = 0;
|
|
ListIt inst_list_it = instList[i].begin();
|
|
|
|
while (inst_list_it != instList[i].end())
|
|
{
|
|
cprintf("Instruction:%i\n",
|
|
num);
|
|
if (!(*inst_list_it)->isSquashed()) {
|
|
if (!(*inst_list_it)->isIssued()) {
|
|
++valid_num;
|
|
cprintf("Count:%i\n", valid_num);
|
|
} else if ((*inst_list_it)->isMemRef() &&
|
|
!(*inst_list_it)->memOpDone) {
|
|
// Loads that have not been marked as executed still count
|
|
// towards the total instructions.
|
|
++valid_num;
|
|
cprintf("Count:%i\n", valid_num);
|
|
}
|
|
}
|
|
|
|
cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
|
"Issued:%i\nSquashed:%i\n",
|
|
(*inst_list_it)->readPC(),
|
|
(*inst_list_it)->seqNum,
|
|
(*inst_list_it)->threadNumber,
|
|
(*inst_list_it)->isIssued(),
|
|
(*inst_list_it)->isSquashed());
|
|
|
|
if ((*inst_list_it)->isMemRef()) {
|
|
cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
|
|
}
|
|
|
|
cprintf("\n");
|
|
|
|
inst_list_it++;
|
|
++num;
|
|
}
|
|
}
|
|
}
|