a8b03e4d01
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
301 lines
9.4 KiB
C++
301 lines
9.4 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/trace.hh"
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#include "base/traceflags.hh"
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#include "cpu/o3/bpred_unit.hh"
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#include <vector>
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#include <list>
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using namespace std;
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template<class Impl>
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TwobitBPredUnit<Impl>::TwobitBPredUnit(Params *params)
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: BP(params->localPredictorSize,
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params->localCtrBits,
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params->instShiftAmt),
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BTB(params->BTBEntries,
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params->BTBTagSize,
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params->instShiftAmt)
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{
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for (int i=0; i < Impl::MaxThreads; i++)
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RAS[i].init(params->RASSize);
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}
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template <class Impl>
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void
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TwobitBPredUnit<Impl>::regStats()
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{
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lookups
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.name(name() + ".BPredUnit.lookups")
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.desc("Number of BP lookups")
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;
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condPredicted
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.name(name() + ".BPredUnit.condPredicted")
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.desc("Number of conditional branches predicted")
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;
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condIncorrect
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.name(name() + ".BPredUnit.condIncorrect")
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.desc("Number of conditional branches incorrect")
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;
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BTBLookups
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.name(name() + ".BPredUnit.BTBLookups")
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.desc("Number of BTB lookups")
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;
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BTBHits
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.name(name() + ".BPredUnit.BTBHits")
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.desc("Number of BTB hits")
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;
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BTBCorrect
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.name(name() + ".BPredUnit.BTBCorrect")
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.desc("Number of correct BTB predictions (this stat may not "
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"work properly.")
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;
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usedRAS
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.name(name() + ".BPredUnit.usedRAS")
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.desc("Number of times the RAS was used to get a target.")
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;
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RASIncorrect
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.name(name() + ".BPredUnit.RASInCorrect")
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.desc("Number of incorrect RAS predictions.")
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;
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}
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template <class Impl>
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bool
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TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
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{
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// See if branch predictor predicts taken.
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// If so, get its target addr either from the BTB or the RAS.
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// Once that's done, speculatively update the predictor?
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// Save off record of branch stuff so the RAS can be fixed
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// up once it's done.
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using TheISA::MachInst;
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bool pred_taken = false;
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Addr target;
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++lookups;
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if (inst->isUncondCtrl()) {
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DPRINTF(Fetch, "BranchPred: [tid:%i] Unconditional control.\n", tid);
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pred_taken = true;
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} else {
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++condPredicted;
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pred_taken = BPLookup(PC);
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Branch predictor predicted %i "
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"for PC %#x\n",
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tid, pred_taken, inst->readPC());
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}
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PredictorHistory predict_record(inst->seqNum, PC, pred_taken, tid);
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// Now lookup in the BTB or RAS.
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if (pred_taken) {
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if (inst->isReturn()) {
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++usedRAS;
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// If it's a function return call, then look up the address
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// in the RAS.
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target = RAS[tid].top();
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// Record the top entry of the RAS, and its index.
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predict_record.usedRAS = true;
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predict_record.RASIndex = RAS[tid].topIdx();
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predict_record.RASTarget = target;
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assert(predict_record.RASIndex < 16);
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RAS[tid].pop();
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x is a return, "
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"RAS predicted target: %#x, RAS index: %i.\n",
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tid, inst->readPC(), target, predict_record.RASIndex);
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} else {
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++BTBLookups;
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if (inst->isCall()) {
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RAS[tid].push(PC + sizeof(MachInst));
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// Record that it was a call so that the top RAS entry can
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// be popped off if the speculation is incorrect.
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predict_record.wasCall = true;
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DPRINTF(Fetch, "BranchPred: [tid:%i] Instruction %#x was a call"
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", adding %#x to the RAS.\n",
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tid, inst->readPC(), PC + sizeof(MachInst));
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}
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if (BTB.valid(PC, tid)) {
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++BTBHits;
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//If it's anything else, use the BTB to get the target addr.
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target = BTB.lookup(PC, tid);
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x predicted"
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" target is %#x.\n",
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tid, inst->readPC(), target);
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} else {
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DPRINTF(Fetch, "BranchPred: [tid:%i]: BTB doesn't have a "
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"valid entry.\n",tid);
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pred_taken = false;
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}
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}
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}
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if (pred_taken) {
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// Set the PC and the instruction's predicted target.
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PC = target;
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inst->setPredTarg(target);
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} else {
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PC = PC + sizeof(MachInst);
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inst->setPredTarg(PC);
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}
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predHist[tid].push_front(predict_record);
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DPRINTF(Fetch, "[tid:%i] predHist.size(): %i\n", tid, predHist[tid].size());
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return pred_taken;
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}
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template <class Impl>
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void
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TwobitBPredUnit<Impl>::update(const InstSeqNum &done_sn, unsigned tid)
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{
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Commiting branches until sequence"
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"number %lli.\n", tid, done_sn);
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while (!predHist[tid].empty() &&
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predHist[tid].back().seqNum <= done_sn) {
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// Update the branch predictor with the correct results.
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BP.update(predHist[tid].back().PC,
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predHist[tid].back().predTaken);
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predHist[tid].pop_back();
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}
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}
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template <class Impl>
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void
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TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, unsigned tid)
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{
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History &pred_hist = predHist[tid];
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while (!pred_hist.empty() &&
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pred_hist.front().seqNum > squashed_sn) {
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if (pred_hist.front().usedRAS) {
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS to: %i,"
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" target: %#x.\n",
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tid,
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pred_hist.front().RASIndex,
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pred_hist.front().RASTarget);
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RAS[tid].restore(pred_hist.front().RASIndex,
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pred_hist.front().RASTarget);
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} else if (pred_hist.front().wasCall) {
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry added "
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"to the RAS.\n",tid);
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RAS[tid].pop();
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}
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pred_hist.pop_front();
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}
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}
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template <class Impl>
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void
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TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
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const Addr &corr_target,
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const bool actually_taken,
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unsigned tid)
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{
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// Now that we know that a branch was mispredicted, we need to undo
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// all the branches that have been seen up until this branch and
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// fix up everything.
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History &pred_hist = predHist[tid];
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++condIncorrect;
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Squashing from sequence number %i, "
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"setting target to %#x.\n",
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tid, squashed_sn, corr_target);
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while (!pred_hist.empty() &&
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pred_hist.front().seqNum > squashed_sn) {
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if (pred_hist.front().usedRAS) {
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS to: %i, "
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"target: %#x.\n",
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tid,
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pred_hist.front().RASIndex,
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pred_hist.front().RASTarget);
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RAS[tid].restore(pred_hist.front().RASIndex,
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pred_hist.front().RASTarget);
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} else if (pred_hist.front().wasCall) {
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry"
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" added to the RAS.\n", tid);
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RAS[tid].pop();
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}
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pred_hist.pop_front();
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}
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// If there's a squash due to a syscall, there may not be an entry
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// corresponding to the squash. In that case, don't bother trying to
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// fix up the entry.
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if (!pred_hist.empty()) {
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pred_hist.front().predTaken = actually_taken;
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if (pred_hist.front().usedRAS) {
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++RASIncorrect;
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}
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BP.update(pred_hist.front().PC, actually_taken);
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BTB.update(pred_hist.front().PC, corr_target, tid);
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}
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}
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