e6c31ceb2b
The L1 cache may have been accessed to provide this data, which confuses it, if it ends up being accesses twice in one cycle. Instead wait 1 tick which will force the timing simple CPU to forward to its next clock cycle when the translation completes. Also prevent multiple outstanding table walks from occuring at once. |
||
|---|---|---|
| .. | ||
| alpha | ||
| arm | ||
| generic | ||
| mips | ||
| power | ||
| sparc | ||
| x86 | ||
| isa_parser.py | ||
| micro_asm.py | ||
| micro_asm_test.py | ||
| SConscript | ||