gem5/src
Marco Elver 9649395f85 cpu, o3: Ignored invalidate causing same-address load reordering
In case the memory subsystem sends a combined response with invalidate
(e.g.  ReadRespWithInvalidate), we cannot ignore the invalidate part
of the response.

If we were to ignore the invalidate part, under certain circumstances
this effectively leads to reordering of loads to the same address
which is not permitted under any memory consistency model implemented
in gem5.

Consider the case where a later load's address is computed before an
earlier load in program order, and is therefore sent to the memory
subsystem first. At some point the earlier load's address is computed
and in doing so correctly marks the later load as a
possibleLoadViolation. In the meantime some other node writes and
sends invalidations to all other nodes. The invalidation races with
the later load's ReadResp, and arrives before ReadResp and is
deferred.  Upon receipt of the ReadResp, the response is changed to
ReadRespWithInvalidate, and sent to the CPU. If we ignore the
invalidate part of the packet, we let the later load read the old
value of the address.  Eventually the earlier load's ReadResp arrives,
but with new data. As there was no invalidate snoop (sunk into the
ReadRespWithInvalidate), and if we did not process the invalidate of
the ReadRespWithInvalidate, we obtain a load reordering.

A similar scenario can be constructed where the earlier load's address
is computed after ReadRespWithInvalidate arrives for the younger
load. In this case hitExternalSnoop needs to be set to true on the
ReadRespWithInvalidate, so that upon knowing the address of the
earlier load, checkViolations will cause the later load to be
squashed.

Finally we must account for the case where both loads are sent to the
memory subsystem (reordered), a snoop invalidate arrives and correctly
sets the later loads fault to ReExec. However, before the CPU
processes the fault, the later load's ReadResp arrives and the
writeback discards the outstanding fault. We must add a check to
ensure that we do not skip any unprocessed faults.
2014-12-02 06:08:03 -05:00
..
arch cpu: Always mask the snoop address when performing lock check 2014-12-02 06:08:00 -05:00
base misc: Another round of static analysis fixups 2014-11-24 09:03:38 -05:00
cpu cpu, o3: Ignored invalidate causing same-address load reordering 2014-12-02 06:08:03 -05:00
dev mem: Remove redundant Packet::allocate calls 2014-12-02 06:07:41 -05:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern misc: Move AddrRangeList from port.hh to addr_range.hh 2014-10-16 05:49:59 -04:00
mem mem: Relax packet src/dest check and shift onus to crossbar 2014-12-02 06:07:56 -05:00
proto mem: change the namespace Message to ProtoMessage 2014-09-01 16:55:46 -05:00
python sim: Sort SimObject descendants and ports 2014-11-12 09:05:21 -05:00
sim misc: Another round of static analysis fixups 2014-11-24 09:03:38 -05:00
unittest unittest: Fix build errors 2014-01-30 12:21:58 -06:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript arch,x86,mem: Dynamically determine the ISA for Ruby store check 2014-10-16 05:49:44 -04:00