Nilay Vaish 3022d463fb ruby: interface with classic memory controller ... This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface.		2014-11-06 05:42:21 -06:00
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Benchmarks.py	arm, tests: Update config files to more recent kernels and create 64-bit regressions.	2014-10-29 23:18:27 -05:00
CacheConfig.py	mem: Rename Bus to XBar to better reflect its behaviour	2014-09-20 17:18:32 -04:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	cpu: `Minor' in-order CPU model	2014-07-23 16:09:04 -05:00
FSConfig.py	arm, tests: Update config files to more recent kernels and create 64-bit regressions.	2014-10-29 23:18:27 -05:00
MemConfig.py	ruby: interface with classic memory controller	2014-11-06 05:42:21 -06:00
O3_ARM_v7a.py	cpu: Change writeback modeling for outstanding instructions	2014-09-03 07:42:33 -04:00
Options.py	arm, tests: Update config files to more recent kernels and create 64-bit regressions.	2014-10-29 23:18:27 -05:00
Simulation.py	config: add num-work-ids command line option	2014-04-10 13:43:33 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00