0495b7e9e7
This patch simply takes a first step to use the NULL ISA build for tests that do not make use of a CPU. Most of the Ruby tests could go the same way, but to avoid duplicating a lot of compilation targets that will have to wait until Ruby is built as a library and linked in independently. --HG-- rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/null/none/memtest/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/null/none/memtest/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/null/none/memtest/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simerr rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
447 lines
8.1 KiB
INI
447 lines
8.1 KiB
INI
[root]
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type=Root
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children=system
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full_system=false
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem l2c membus physmem toL2Bus
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boot_osflags=a
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clock=1000
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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mem_mode=timing
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mem_ranges=
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memories=system.funcmem system.physmem
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num_work_ids=16
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[1]
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[system.cpu0]
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type=MemTest
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children=l1c
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atomic=false
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clock=500
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[0]
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test=system.cpu0.l1c.cpu_side
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[system.cpu0.l1c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.test
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mem_side=system.toL2Bus.slave[0]
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[system.cpu1]
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type=MemTest
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children=l1c
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atomic=false
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clock=500
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[1]
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test=system.cpu1.l1c.cpu_side
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[system.cpu1.l1c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.test
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mem_side=system.toL2Bus.slave[1]
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[system.cpu2]
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type=MemTest
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children=l1c
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atomic=false
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clock=500
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[2]
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test=system.cpu2.l1c.cpu_side
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[system.cpu2.l1c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu2.test
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mem_side=system.toL2Bus.slave[2]
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[system.cpu3]
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type=MemTest
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children=l1c
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atomic=false
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clock=500
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[3]
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test=system.cpu3.l1c.cpu_side
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[system.cpu3.l1c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu3.test
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mem_side=system.toL2Bus.slave[3]
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[system.cpu4]
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type=MemTest
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children=l1c
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atomic=false
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clock=500
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[4]
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test=system.cpu4.l1c.cpu_side
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[system.cpu4.l1c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu4.test
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mem_side=system.toL2Bus.slave[4]
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[system.cpu5]
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type=MemTest
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children=l1c
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atomic=false
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clock=500
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[5]
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test=system.cpu5.l1c.cpu_side
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[system.cpu5.l1c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu5.test
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mem_side=system.toL2Bus.slave[5]
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[system.cpu6]
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type=MemTest
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children=l1c
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atomic=false
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clock=500
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[6]
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test=system.cpu6.l1c.cpu_side
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[system.cpu6.l1c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu6.test
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mem_side=system.toL2Bus.slave[6]
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[system.cpu7]
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type=MemTest
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children=l1c
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atomic=false
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clock=500
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[7]
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test=system.cpu7.l1c.cpu_side
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[system.cpu7.l1c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu7.test
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mem_side=system.toL2Bus.slave[7]
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[system.funcbus]
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type=NoncoherentBus
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block_size=64
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clock=1000
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header_cycles=1
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use_default_range=false
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width=8
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master=system.funcmem.port
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slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
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[system.funcmem]
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type=SimpleMemory
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bandwidth=73.000000
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clock=1000
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conf_table_reported=false
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in_addr_map=false
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.funcbus.master[0]
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[system.l2c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=8
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block_size=64
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clock=500
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forward_snoops=true
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hit_latency=20
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is_top_level=false
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max_miss_count=0
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mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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response_latency=20
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size=65536
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system=system
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tgts_per_mshr=12
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two_queue=false
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write_buffers=8
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cpu_side=system.toL2Bus.master[0]
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mem_side=system.membus.slave[0]
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[system.membus]
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type=CoherentBus
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block_size=64
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clock=1000
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header_cycles=1
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system=system
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use_default_range=false
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width=16
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master=system.physmem.port
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slave=system.l2c.mem_side system.system_port
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[system.physmem]
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type=SimpleMemory
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bandwidth=73.000000
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clock=1000
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conf_table_reported=false
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in_addr_map=true
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.master[0]
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[system.toL2Bus]
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type=CoherentBus
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block_size=64
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clock=500
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header_cycles=1
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system=system
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use_default_range=false
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width=16
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master=system.l2c.cpu_side
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slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
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