gem5/cpu/beta_cpu/decode.hh
Kevin Lim 61d95de4c8 Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-03 10:56:47 -04:00

149 lines
4.1 KiB
C++

// Todo:
// Add a couple of the branch fields to DynInst. Figure out where DynInst
// should try to compute the target of a PC-relative branch. Try to avoid
// having so many returns within the code.
// Fix up squashing too, as it's too
// dependent upon the iew stage continually telling it to squash.
#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
#include <queue>
#include "base/statistics.hh"
#include "base/timebuf.hh"
template<class Impl>
class SimpleDecode
{
private:
// Typedefs from the Impl.
typedef typename Impl::ISA ISA;
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params;
typedef typename Impl::CPUPol CPUPol;
// Typedefs from the CPU policy.
typedef typename CPUPol::FetchStruct FetchStruct;
typedef typename CPUPol::DecodeStruct DecodeStruct;
typedef typename CPUPol::TimeStruct TimeStruct;
// Typedefs from the ISA.
typedef typename ISA::Addr Addr;
public:
// The only time decode will become blocked is if dispatch becomes
// blocked, which means IQ or ROB is probably full.
enum Status {
Running,
Idle,
Squashing,
Blocked,
Unblocking
};
private:
// May eventually need statuses on a per thread basis.
Status _status;
public:
SimpleDecode(Params &params);
void regStats();
void setCPU(FullCPU *cpu_ptr);
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
void tick();
void decode();
// Might want to make squash a friend function.
void squash();
private:
inline bool fetchInstsValid();
void block();
inline void unblock();
void squash(DynInstPtr &inst);
void dumpFetchQueue();
// Interfaces to objects outside of decode.
/** CPU interface. */
FullCPU *cpu;
/** Time buffer interface. */
TimeBuffer<TimeStruct> *timeBuffer;
/** Wire to get rename's output from backwards time buffer. */
typename TimeBuffer<TimeStruct>::wire fromRename;
/** Wire to get iew's information from backwards time buffer. */
typename TimeBuffer<TimeStruct>::wire fromIEW;
/** Wire to get commit's information from backwards time buffer. */
typename TimeBuffer<TimeStruct>::wire fromCommit;
/** Wire to write information heading to previous stages. */
// Might not be the best name as not only fetch will read it.
typename TimeBuffer<TimeStruct>::wire toFetch;
/** Decode instruction queue. */
TimeBuffer<DecodeStruct> *decodeQueue;
/** Wire used to write any information heading to rename. */
typename TimeBuffer<DecodeStruct>::wire toRename;
/** Fetch instruction queue interface. */
TimeBuffer<FetchStruct> *fetchQueue;
/** Wire to get fetch's output from fetch queue. */
typename TimeBuffer<FetchStruct>::wire fromFetch;
/** Skid buffer between fetch and decode. */
std::queue<FetchStruct> skidBuffer;
private:
//Consider making these unsigned to avoid any confusion.
/** Rename to decode delay, in ticks. */
unsigned renameToDecodeDelay;
/** IEW to decode delay, in ticks. */
unsigned iewToDecodeDelay;
/** Commit to decode delay, in ticks. */
unsigned commitToDecodeDelay;
/** Fetch to decode delay, in ticks. */
unsigned fetchToDecodeDelay;
/** The width of decode, in instructions. */
unsigned decodeWidth;
/** The instruction that decode is currently on. It needs to have
* persistent state so that when a stall occurs in the middle of a
* group of instructions, it can restart at the proper instruction.
*/
unsigned numInst;
Stats::Scalar<> decodeIdleCycles;
Stats::Scalar<> decodeBlockedCycles;
Stats::Scalar<> decodeUnblockCycles;
Stats::Scalar<> decodeSquashCycles;
Stats::Scalar<> decodeBranchMispred;
Stats::Scalar<> decodeControlMispred;
Stats::Scalar<> decodeDecodedInsts;
Stats::Scalar<> decodeSquashedInsts;
};
#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__