61d95de4c8
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
Remove OOO CPU stuff.
arch/alpha/faults.hh:
Add fake memory fault. This will be removed eventually.
arch/alpha/isa_desc:
Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
Remove asid.
cpu/beta_cpu/comm.hh:
Remove global history field.
cpu/beta_cpu/commit.hh:
Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
Add debug function.
cpu/beta_cpu/decode_impl.hh:
Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
Extra forward declares added due to compile error.
--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
135 lines
2.6 KiB
C++
135 lines
2.6 KiB
C++
#ifndef __ALPHA_SIMPLE_PARAMS_HH__
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#define __ALPHA_SIMPLE_PARAMS_HH__
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#include "cpu/beta_cpu/full_cpu.hh"
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//Forward declarations
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class System;
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class AlphaITB;
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class AlphaDTB;
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class FunctionalMemory;
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class Process;
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class MemInterface;
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/**
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* This file defines the parameters that will be used for the AlphaFullCPU.
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* This must be defined externally so that the Impl can have a params class
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* defined that it can pass to all of the individual stages.
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*/
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class AlphaSimpleParams : public BaseFullCPU::Params
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{
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public:
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#ifdef FULL_SYSTEM
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AlphaITB *itb; AlphaDTB *dtb;
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#else
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std::vector<Process *> workload;
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Process *process;
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#endif // FULL_SYSTEM
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FunctionalMemory *mem;
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//
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// Caches
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//
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MemInterface *icacheInterface;
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MemInterface *dcacheInterface;
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//
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// Fetch
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//
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unsigned decodeToFetchDelay;
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unsigned renameToFetchDelay;
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unsigned iewToFetchDelay;
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unsigned commitToFetchDelay;
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unsigned fetchWidth;
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//
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// Decode
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//
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unsigned renameToDecodeDelay;
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unsigned iewToDecodeDelay;
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unsigned commitToDecodeDelay;
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unsigned fetchToDecodeDelay;
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unsigned decodeWidth;
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//
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// Rename
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//
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unsigned iewToRenameDelay;
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unsigned commitToRenameDelay;
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unsigned decodeToRenameDelay;
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unsigned renameWidth;
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//
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// IEW
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//
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unsigned commitToIEWDelay;
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unsigned renameToIEWDelay;
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unsigned issueToExecuteDelay;
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unsigned issueWidth;
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unsigned executeWidth;
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unsigned executeIntWidth;
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unsigned executeFloatWidth;
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unsigned executeBranchWidth;
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unsigned executeMemoryWidth;
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//
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// Commit
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//
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unsigned iewToCommitDelay;
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unsigned renameToROBDelay;
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unsigned commitWidth;
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unsigned squashWidth;
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//
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// Branch predictor (BP & BTB)
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//
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/*
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unsigned localPredictorSize;
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unsigned localPredictorCtrBits;
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*/
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unsigned local_predictor_size;
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unsigned local_ctr_bits;
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unsigned local_history_table_size;
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unsigned local_history_bits;
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unsigned global_predictor_size;
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unsigned global_ctr_bits;
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unsigned global_history_bits;
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unsigned choice_predictor_size;
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unsigned choice_ctr_bits;
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unsigned BTBEntries;
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unsigned BTBTagSize;
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unsigned RASSize;
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//
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// Load store queue
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//
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unsigned LQEntries;
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unsigned SQEntries;
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//
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// Memory dependence
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//
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unsigned SSITSize;
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unsigned LFSTSize;
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//
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// Miscellaneous
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//
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unsigned numPhysIntRegs;
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unsigned numPhysFloatRegs;
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unsigned numIQEntries;
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unsigned numROBEntries;
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// Probably can get this from somewhere.
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unsigned instShiftAmt;
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bool defReg;
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};
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#endif
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