447 lines
22 KiB
C++
447 lines
22 KiB
C++
/*****************************************************************************
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* McPAT
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2012 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include <algorithm>
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#include <cassert>
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#include <cmath>
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#include <iostream>
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#include <string>
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#include "XML_Parse.h"
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#include "basic_circuit.h"
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#include "basic_components.h"
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#include "const.h"
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#include "io.h"
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#include "iocontrollers.h"
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#include "logic.h"
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#include "parameter.h"
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/*
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SUN Niagara 2 I/O power analysis:
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total signal bits: 711
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Total FBDIMM bits: (14+10)*2*8= 384
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PCIe bits: (8 + 8)*2 = 32
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10Gb NIC: (4*2+4*2)*2 = 32
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Debug I/Os: 168
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Other I/Os: 711- 32-32 - 384 - 168 = 95
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According to "Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip"
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90% of I/Os are SerDers (the calucaltion is 384+64/(711-168)=83% about the same as the 90% reported in the paper)
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--> around 80Pins are common I/Os.
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Common I/Os consumes 71mW/Gb/s according to Cadence ChipEstimate @65nm
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Niagara 2 I/O clock is 1/4 of core clock. --> 87pin (<--((711-168)*17%)) * 71mW/Gb/s *0.25*1.4Ghz = 2.17W
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Total dynamic power of FBDIMM, NIC, PCIe = 84*0.132 + 84*0.049*0.132 = 11.14 - 2.17 = 8.98
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Further, if assuming I/O logic power is about 50% of I/Os then Total energy of FBDIMM, NIC, PCIe = 11.14 - 2.17*1.5 = 7.89
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*/
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/*
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* A bug in Cadence ChipEstimator: After update the clock rate in the clock tab, a user
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* need to re-select the IP clock (the same clk) and then click Estimate. if not reselect
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* the new clock rate may not be propogate into the IPs.
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*
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*/
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NIUController::NIUController(ParseXML *XML_interface,InputParameter* interface_ip_)
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:XML(XML_interface),
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interface_ip(*interface_ip_)
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{
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local_result = init_interface(&interface_ip);
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double frontend_area, phy_area, mac_area, SerDer_area;
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double frontend_dyn, mac_dyn, SerDer_dyn;
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double frontend_gates, mac_gates, SerDer_gates;
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double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio();
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double NMOS_sizing, PMOS_sizing;
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set_niu_param();
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if (niup.type == 0) //high performance NIU
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{
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//Area estimation based on average of die photo from Niagara 2 and Cadence ChipEstimate using 65nm.
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mac_area = (1.53 + 0.3)/2 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
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//Area estimation based on average of die photo from Niagara 2, ISSCC "An 800mW 10Gb Ethernet Transceiver in 0.13μm CMOS"
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//and"A 1.2-V-Only 900-mW 10 Gb Ethernet Transceiver and XAUI Interface With Robust VCO Tuning Technique" Frontend is PCS
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frontend_area = (9.8 + (6 + 18)*65/130*65/130)/3 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
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//Area estimation based on average of die photo from Niagara 2 and Cadence ChipEstimate hard IP @65nm.
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//SerDer is very hard to scale
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SerDer_area = (1.39 + 0.36) * (interface_ip.F_sz_um/0.065);//* (interface_ip.F_sz_um/0.065);
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phy_area = frontend_area + SerDer_area;
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//total area
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area.set_area((mac_area + frontend_area + SerDer_area)*1e6);
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//Power
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//Cadence ChipEstimate using 65nm (mac, front_end are all energy. E=P*T = P/F = 1.37/1Ghz = 1.37e-9);
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mac_dyn = 2.19e-9*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);//niup.clockRate; //2.19W@1GHz fully active according to Cadence ChipEstimate @65nm
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//Cadence ChipEstimate using 65nm soft IP;
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frontend_dyn = 0.27e-9*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);//niup.clockRate;
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//according to "A 100mW 9.6Gb/s Transceiver in 90nm CMOS..." ISSCC 2006
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//SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm
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SerDer_dyn = 0.01*10*sqrt(interface_ip.F_sz_um/0.09)*g_tp.peri_global.Vdd/1.2*g_tp.peri_global.Vdd/1.2;
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SerDer_dyn /= niup.clockRate;//covert to energy per clock cycle of whole NIU
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//Cadence ChipEstimate using 65nm
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mac_gates = 111700;
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frontend_gates = 320000;
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SerDer_gates = 200000;
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NMOS_sizing = 5*g_tp.min_w_nmos_;
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PMOS_sizing = 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r;
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}
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else
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{//Low power implementations are mostly from Cadence ChipEstimator; Ignore the multiple IP effect
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// ---When there are multiple IP (same kind or not) selected, Cadence ChipEstimator results are not
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// a simple summation of all IPs. Ignore this effect
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mac_area = 0.24 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
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frontend_area = 0.1 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);//Frontend is the PCS layer
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SerDer_area = 0.35 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
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//Compare 130um implementation in "A 1.2-V-Only 900-mW 10 Gb Ethernet Transceiver and XAUI Interface With Robust VCO Tuning Technique"
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//and the ChipEstimator XAUI PHY hard IP, confirm that even PHY can scale perfectly with the technology
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//total area
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area.set_area((mac_area + frontend_area + SerDer_area)*1e6);
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//Power
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//Cadence ChipEstimate using 65nm (mac, front_end are all energy. E=P*T = P/F = 1.37/1Ghz = 1.37e-9);
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mac_dyn = 1.257e-9*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);//niup.clockRate; //2.19W@1GHz fully active according to Cadence ChipEstimate @65nm
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//Cadence ChipEstimate using 65nm soft IP;
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frontend_dyn = 0.6e-9*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);//niup.clockRate;
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//SerDer_dyn is power not energy, scaling from 216mw/10Gb/s @130nm
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SerDer_dyn = 0.0216*10*(interface_ip.F_sz_um/0.13)*g_tp.peri_global.Vdd/1.2*g_tp.peri_global.Vdd/1.2;
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SerDer_dyn /= niup.clockRate;//covert to energy per clock cycle of whole NIU
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mac_gates = 111700;
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frontend_gates = 52000;
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SerDer_gates = 199260;
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NMOS_sizing = g_tp.min_w_nmos_;
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PMOS_sizing = g_tp.min_w_nmos_*pmos_to_nmos_sizing_r;
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}
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power_t.readOp.dynamic = mac_dyn + frontend_dyn + SerDer_dyn;
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power_t.readOp.leakage = (mac_gates + frontend_gates + frontend_gates)*cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand)*g_tp.peri_global.Vdd;//unit W
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double long_channel_device_reduction = longer_channel_device_reduction(Uncore_device);
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power_t.readOp.longer_channel_leakage = power_t.readOp.leakage * long_channel_device_reduction;
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power_t.readOp.gate_leakage = (mac_gates + frontend_gates + frontend_gates)*cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand)*g_tp.peri_global.Vdd;//unit W
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}
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void NIUController::computeEnergy(bool is_tdp)
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{
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if (is_tdp)
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{
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power = power_t;
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power.readOp.dynamic *= niup.duty_cycle;
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}
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else
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{
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rt_power = power_t;
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rt_power.readOp.dynamic *= niup.perc_load;
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}
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}
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void NIUController::displayEnergy(uint32_t indent,int plevel,bool is_tdp)
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{
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string indent_str(indent, ' ');
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string indent_str_next(indent+2, ' ');
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bool long_channel = XML->sys.longer_channel_device;
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if (is_tdp)
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{
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cout << "NIU:" << endl;
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cout << indent_str<< "Area = " << area.get_area()*1e-6<< " mm^2" << endl;
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cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic*niup.clockRate << " W" << endl;
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cout << indent_str<< "Subthreshold Leakage = "
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<< (long_channel? power.readOp.longer_channel_leakage:power.readOp.leakage) <<" W" << endl;
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//cout << indent_str<< "Subthreshold Leakage = " << power.readOp.longer_channel_leakage <<" W" << endl;
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cout << indent_str<< "Gate Leakage = " << power.readOp.gate_leakage << " W" << endl;
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cout << indent_str << "Runtime Dynamic = " << rt_power.readOp.dynamic*niup.clockRate << " W" << endl;
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cout<<endl;
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}
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else
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{
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}
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}
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void NIUController::set_niu_param()
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{
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niup.clockRate = XML->sys.niu.clockrate;
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niup.clockRate *= 1e6;
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niup.num_units = XML->sys.niu.number_units;
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niup.duty_cycle = XML->sys.niu.duty_cycle;
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niup.perc_load = XML->sys.niu.total_load_perc;
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niup.type = XML->sys.niu.type;
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// niup.executionTime = XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
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}
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PCIeController::PCIeController(ParseXML *XML_interface,InputParameter* interface_ip_)
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:XML(XML_interface),
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interface_ip(*interface_ip_)
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{
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local_result = init_interface(&interface_ip);
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double frontend_area, phy_area, ctrl_area, SerDer_area;
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double ctrl_dyn, frontend_dyn, SerDer_dyn;
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double ctrl_gates,frontend_gates, SerDer_gates;
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double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio();
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double NMOS_sizing, PMOS_sizing;
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/* Assuming PCIe is bit-slice based architecture
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* This is the reason for /8 in both area and power calculation
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* to get per lane numbers
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*/
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set_pcie_param();
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if (pciep.type == 0) //high performance NIU
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{
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//Area estimation based on average of die photo from Niagara 2 and Cadence ChipEstimate @ 65nm.
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ctrl_area = (5.2 + 0.5)/2 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
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//Area estimation based on average of die photo from Niagara 2, and Cadence ChipEstimate @ 65nm.
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frontend_area = (5.2 + 0.1)/2 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
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//Area estimation based on average of die photo from Niagara 2 and Cadence ChipEstimate hard IP @65nm.
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//SerDer is very hard to scale
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SerDer_area = (3.03 + 0.36) * (interface_ip.F_sz_um/0.065);//* (interface_ip.F_sz_um/0.065);
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phy_area = frontend_area + SerDer_area;
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//total area
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//Power
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//Cadence ChipEstimate using 65nm the controller includes everything: the PHY, the data link and transaction layer
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ctrl_dyn = 3.75e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);
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// //Cadence ChipEstimate using 65nm soft IP;
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// frontend_dyn = 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);
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//SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm
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SerDer_dyn = 0.01*4*(interface_ip.F_sz_um/0.09)*g_tp.peri_global.Vdd/1.2*g_tp.peri_global.Vdd/1.2;//PCIe 2.0 max per lane speed is 4Gb/s
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SerDer_dyn /= pciep.clockRate;//covert to energy per clock cycle
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//power_t.readOp.dynamic = (ctrl_dyn)*pciep.num_channels;
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//Cadence ChipEstimate using 65nm
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ctrl_gates = 900000/8*pciep.num_channels;
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// frontend_gates = 120000/8;
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// SerDer_gates = 200000/8;
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NMOS_sizing = 5*g_tp.min_w_nmos_;
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PMOS_sizing = 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r;
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}
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else
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{
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ctrl_area = 0.412 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
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//Area estimation based on average of die photo from Niagara 2, and Cadence ChipEstimate @ 65nm.
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SerDer_area = 0.36 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
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//total area
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//Power
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//Cadence ChipEstimate using 65nm the controller includes everything: the PHY, the data link and transaction layer
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ctrl_dyn = 2.21e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);
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// //Cadence ChipEstimate using 65nm soft IP;
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// frontend_dyn = 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);
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//SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm
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SerDer_dyn = 0.01*4*(interface_ip.F_sz_um/0.09)*g_tp.peri_global.Vdd/1.2*g_tp.peri_global.Vdd/1.2;//PCIe 2.0 max per lane speed is 4Gb/s
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SerDer_dyn /= pciep.clockRate;//covert to energy per clock cycle
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//Cadence ChipEstimate using 65nm
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ctrl_gates = 200000/8*pciep.num_channels;
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// frontend_gates = 120000/8;
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SerDer_gates = 200000/8*pciep.num_channels;
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NMOS_sizing = g_tp.min_w_nmos_;
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PMOS_sizing = g_tp.min_w_nmos_*pmos_to_nmos_sizing_r;
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}
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area.set_area(((ctrl_area + (pciep.withPHY? SerDer_area:0))/8*pciep.num_channels)*1e6);
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power_t.readOp.dynamic = (ctrl_dyn + (pciep.withPHY? SerDer_dyn:0))*pciep.num_channels;
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power_t.readOp.leakage = (ctrl_gates + (pciep.withPHY? SerDer_gates:0))*cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand)*g_tp.peri_global.Vdd;//unit W
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double long_channel_device_reduction = longer_channel_device_reduction(Uncore_device);
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power_t.readOp.longer_channel_leakage = power_t.readOp.leakage * long_channel_device_reduction;
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power_t.readOp.gate_leakage = (ctrl_gates + (pciep.withPHY? SerDer_gates:0))*cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand)*g_tp.peri_global.Vdd;//unit W
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}
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void PCIeController::computeEnergy(bool is_tdp)
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{
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if (is_tdp)
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{
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power = power_t;
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power.readOp.dynamic *= pciep.duty_cycle;
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}
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else
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{
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rt_power = power_t;
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rt_power.readOp.dynamic *= pciep.perc_load;
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}
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}
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void PCIeController::displayEnergy(uint32_t indent,int plevel,bool is_tdp)
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{
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string indent_str(indent, ' ');
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string indent_str_next(indent+2, ' ');
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bool long_channel = XML->sys.longer_channel_device;
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if (is_tdp)
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{
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cout << "PCIe:" << endl;
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cout << indent_str<< "Area = " << area.get_area()*1e-6<< " mm^2" << endl;
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cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic*pciep.clockRate << " W" << endl;
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cout << indent_str<< "Subthreshold Leakage = "
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<< (long_channel? power.readOp.longer_channel_leakage:power.readOp.leakage) <<" W" << endl;
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//cout << indent_str<< "Subthreshold Leakage = " << power.readOp.longer_channel_leakage <<" W" << endl;
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cout << indent_str<< "Gate Leakage = " << power.readOp.gate_leakage << " W" << endl;
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cout << indent_str << "Runtime Dynamic = " << rt_power.readOp.dynamic*pciep.clockRate << " W" << endl;
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cout<<endl;
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}
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else
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{
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}
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}
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void PCIeController::set_pcie_param()
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{
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pciep.clockRate = XML->sys.pcie.clockrate;
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pciep.clockRate *= 1e6;
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pciep.num_units = XML->sys.pcie.number_units;
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pciep.num_channels = XML->sys.pcie.num_channels;
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pciep.duty_cycle = XML->sys.pcie.duty_cycle;
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pciep.perc_load = XML->sys.pcie.total_load_perc;
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pciep.type = XML->sys.pcie.type;
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pciep.withPHY = XML->sys.pcie.withPHY;
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// pciep.executionTime = XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
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}
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FlashController::FlashController(ParseXML *XML_interface,InputParameter* interface_ip_)
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:XML(XML_interface),
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interface_ip(*interface_ip_)
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{
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local_result = init_interface(&interface_ip);
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double frontend_area, phy_area, ctrl_area, SerDer_area;
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double ctrl_dyn, frontend_dyn, SerDer_dyn;
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double ctrl_gates,frontend_gates, SerDer_gates;
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double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio();
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double NMOS_sizing, PMOS_sizing;
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/* Assuming PCIe is bit-slice based architecture
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* This is the reason for /8 in both area and power calculation
|
|
* to get per lane numbers
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|
*/
|
|
|
|
set_fc_param();
|
|
if (fcp.type == 0) //high performance NIU
|
|
{
|
|
cout<<"Current McPAT does not support high performance flash contorller since even low power designs are enough for maintain throughput"<<endl;
|
|
exit(0);
|
|
NMOS_sizing = 5*g_tp.min_w_nmos_;
|
|
PMOS_sizing = 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r;
|
|
}
|
|
else
|
|
{
|
|
ctrl_area = 0.243 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
|
|
//Area estimation based on Cadence ChipEstimate @ 65nm: NANDFLASH-CTRL from CAST
|
|
SerDer_area = 0.36/8 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
|
|
//based On PCIe PHY TSMC65GP from Cadence ChipEstimate @ 65nm, it support 8x lanes with each lane
|
|
//speed up to 250MB/s (PCIe1.1x) This is already saturate the 200MB/s of the flash controller core above.
|
|
ctrl_gates = 129267;
|
|
SerDer_gates = 200000/8;
|
|
NMOS_sizing = g_tp.min_w_nmos_;
|
|
PMOS_sizing = g_tp.min_w_nmos_*pmos_to_nmos_sizing_r;
|
|
|
|
//Power
|
|
//Cadence ChipEstimate using 65nm the controller 125mW for every 200MB/s This is power not energy!
|
|
ctrl_dyn = 0.125*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);
|
|
//SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm
|
|
SerDer_dyn = 0.01*1.6*(interface_ip.F_sz_um/0.09)*g_tp.peri_global.Vdd/1.2*g_tp.peri_global.Vdd/1.2;
|
|
//max Per controller speed is 1.6Gb/s (200MB/s)
|
|
}
|
|
double number_channel = 1+(fcp.num_channels-1)*0.2;
|
|
area.set_area((ctrl_area + (fcp.withPHY? SerDer_area:0))*1e6*number_channel);
|
|
power_t.readOp.dynamic = (ctrl_dyn + (fcp.withPHY? SerDer_dyn:0))*number_channel;
|
|
power_t.readOp.leakage = ((ctrl_gates + (fcp.withPHY? SerDer_gates:0))*number_channel)*cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand)*g_tp.peri_global.Vdd;//unit W
|
|
double long_channel_device_reduction = longer_channel_device_reduction(Uncore_device);
|
|
power_t.readOp.longer_channel_leakage = power_t.readOp.leakage * long_channel_device_reduction;
|
|
power_t.readOp.gate_leakage = ((ctrl_gates + (fcp.withPHY? SerDer_gates:0))*number_channel)*cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand)*g_tp.peri_global.Vdd;//unit W
|
|
}
|
|
|
|
void FlashController::computeEnergy(bool is_tdp)
|
|
{
|
|
if (is_tdp)
|
|
{
|
|
|
|
|
|
power = power_t;
|
|
power.readOp.dynamic *= fcp.duty_cycle;
|
|
|
|
}
|
|
else
|
|
{
|
|
rt_power = power_t;
|
|
rt_power.readOp.dynamic *= fcp.perc_load;
|
|
}
|
|
}
|
|
|
|
void FlashController::displayEnergy(uint32_t indent,int plevel,bool is_tdp)
|
|
{
|
|
string indent_str(indent, ' ');
|
|
string indent_str_next(indent+2, ' ');
|
|
bool long_channel = XML->sys.longer_channel_device;
|
|
|
|
if (is_tdp)
|
|
{
|
|
cout << "Flash Controller:" << endl;
|
|
cout << indent_str<< "Area = " << area.get_area()*1e-6<< " mm^2" << endl;
|
|
cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic << " W" << endl;//no multiply of clock since this is power already
|
|
cout << indent_str<< "Subthreshold Leakage = "
|
|
<< (long_channel? power.readOp.longer_channel_leakage:power.readOp.leakage) <<" W" << endl;
|
|
//cout << indent_str<< "Subthreshold Leakage = " << power.readOp.longer_channel_leakage <<" W" << endl;
|
|
cout << indent_str<< "Gate Leakage = " << power.readOp.gate_leakage << " W" << endl;
|
|
cout << indent_str << "Runtime Dynamic = " << rt_power.readOp.dynamic << " W" << endl;
|
|
cout<<endl;
|
|
}
|
|
else
|
|
{
|
|
|
|
}
|
|
|
|
}
|
|
|
|
void FlashController::set_fc_param()
|
|
{
|
|
// fcp.clockRate = XML->sys.flashc.mc_clock;
|
|
// fcp.clockRate *= 1e6;
|
|
fcp.peakDataTransferRate = XML->sys.flashc.peak_transfer_rate;
|
|
fcp.num_channels = ceil(fcp.peakDataTransferRate/200);
|
|
fcp.num_mcs = XML->sys.flashc.number_mcs;
|
|
fcp.duty_cycle = XML->sys.flashc.duty_cycle;
|
|
fcp.perc_load = XML->sys.flashc.total_load_perc;
|
|
fcp.type = XML->sys.flashc.type;
|
|
fcp.withPHY = XML->sys.flashc.withPHY;
|
|
// flashcp.executionTime = XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
|
|
|
|
}
|