613 lines
19 KiB
C++
613 lines
19 KiB
C++
/*****************************************************************************
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* McPAT/CACTI
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2012 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include <cassert>
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#include "Ucache.h"
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#include "nuca.h"
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unsigned int MIN_BANKSIZE=65536;
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#define FIXED_OVERHEAD 55e-12 /* clock skew and jitter in s. Ref: Hrishikesh et al ISCA 01 */
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#define LATCH_DELAY 28e-12 /* latch delay in s (later should use FO4 TODO) */
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#define CONTR_2_BANK_LAT 0
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int cont_stats[2 /*l2 or l3*/][5/* cores */][ROUTER_TYPES][7 /*banks*/][8 /* cycle time */];
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Nuca::Nuca(
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TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)
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):deviceType(dt)
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{
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init_cont();
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}
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void
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Nuca::init_cont()
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{
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FILE *cont;
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char line[5000];
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char jk[5000];
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cont = fopen("contention.dat", "r");
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if (!cont) {
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cout << "contention.dat file is missing!\n";
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exit(0);
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}
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for(int i=0; i<2; i++) {
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for(int j=2; j<5; j++) {
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for(int k=0; k<ROUTER_TYPES; k++) {
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for(int l=0;l<7; l++) {
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int *temp = cont_stats[i/*l2 or l3*/][j/*core*/][k/*64 or 128 or 256 link bw*/][l /* no banks*/];
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assert(fscanf(cont, "%[^\n]\n", line) != EOF);
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sscanf(line, "%[^:]: %d %d %d %d %d %d %d %d",jk, &temp[0], &temp[1], &temp[2], &temp[3],
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&temp[4], &temp[5], &temp[6], &temp[7]);
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}
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}
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}
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}
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fclose(cont);
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}
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void
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Nuca::print_cont_stats()
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{
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for(int i=0; i<2; i++) {
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for(int j=2; j<5; j++) {
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for(int k=0; k<ROUTER_TYPES; k++) {
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for(int l=0;l<7; l++) {
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for(int m=0;l<7; l++) {
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cout << cont_stats[i][j][k][l][m] << " ";
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}
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cout << endl;
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}
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}
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}
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}
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cout << endl;
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}
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Nuca::~Nuca(){
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for (int i = wt_min; i <= wt_max; i++) {
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delete wire_vertical[i];
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delete wire_horizontal[i];
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}
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}
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/* converts latency (in s) to cycles depending upon the FREQUENCY (in GHz) */
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int
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Nuca::calc_cycles(double lat, double oper_freq)
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{
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//TODO: convert latch delay to FO4 */
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double cycle_time = (1.0/(oper_freq*1e9)); /*s*/
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cycle_time -= LATCH_DELAY;
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cycle_time -= FIXED_OVERHEAD;
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return (int)ceil(lat/cycle_time);
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}
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nuca_org_t::~nuca_org_t() {
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// if(h_wire) delete h_wire;
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// if(v_wire) delete v_wire;
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// if(router) delete router;
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}
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/*
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* Version - 6.0
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*
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* Perform exhaustive search across different bank organizatons,
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* router configurations, grid organizations, and wire models and
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* find an optimal NUCA organization
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* For different bank count values
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* 1. Optimal bank organization is calculated
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* 2. For each bank organization, find different NUCA organizations
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* using various router configurations, grid organizations,
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* and wire models.
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* 3. NUCA model with the least cost is picked for
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* this particular bank count
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* Finally include contention statistics and find the optimal
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* NUCA configuration
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*/
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void
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Nuca::sim_nuca()
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{
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/* temp variables */
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int it, ro, wr;
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int num_cyc;
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unsigned int i, j, k;
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unsigned int r, c;
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int l2_c;
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int bank_count = 0;
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uca_org_t ures;
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nuca_org_t *opt_n;
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mem_array tag, data;
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list<nuca_org_t *> nuca_list;
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Router *router_s[ROUTER_TYPES];
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router_s[0] = new Router(64.0, 8, 4, &(g_tp.peri_global));
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router_s[0]->print_router();
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router_s[1] = new Router(128.0, 8, 4, &(g_tp.peri_global));
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router_s[1]->print_router();
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router_s[2] = new Router(256.0, 8, 4, &(g_tp.peri_global));
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router_s[2]->print_router();
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int core_in; // to store no. of cores
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/* to search diff grid organizations */
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double curr_hop, totno_hops, totno_hhops, totno_vhops, tot_lat,
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curr_acclat;
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double avg_lat, avg_hop, avg_hhop, avg_vhop, avg_dyn_power,
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avg_leakage_power;
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double opt_acclat = INF, opt_avg_lat = INF, opt_tot_lat = INF;
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int opt_rows = 0;
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int opt_columns = 0;
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double opt_totno_hops = 0;
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double opt_avg_hop = 0;
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double opt_dyn_power = 0, opt_leakage_power = 0;
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min_values_t minval;
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int bank_start = 0;
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int flit_width = 0;
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/* vertical and horizontal hop latency values */
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int ver_hop_lat, hor_hop_lat; /* in cycles */
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/* no. of different bank sizes to consider */
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int iterations;
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g_ip->nuca_cache_sz = g_ip->cache_sz;
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nuca_list.push_back(new nuca_org_t());
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if (g_ip->cache_level == 0) l2_c = 1;
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else l2_c = 0;
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if (g_ip->cores <= 4) core_in = 2;
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else if (g_ip->cores <= 8) core_in = 3;
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else if (g_ip->cores <= 16) core_in = 4;
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else {cout << "Number of cores should be <= 16!\n"; exit(0);}
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// set the lower bound to an appropriate value. this depends on cache associativity
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if (g_ip->assoc > 2) {
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i = 2;
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while (i != g_ip->assoc) {
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MIN_BANKSIZE *= 2;
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i *= 2;
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}
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}
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iterations = (int)logtwo((int)g_ip->cache_sz/MIN_BANKSIZE);
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if (g_ip->force_wiretype)
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{
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if (g_ip->wt == Low_swing) {
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wt_min = Low_swing;
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wt_max = Low_swing;
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}
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else {
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wt_min = Global;
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wt_max = Low_swing-1;
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}
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}
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else {
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wt_min = Global;
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wt_max = Low_swing;
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}
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if (g_ip->nuca_bank_count != 0) { // simulate just one bank
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if (g_ip->nuca_bank_count != 2 && g_ip->nuca_bank_count != 4 &&
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g_ip->nuca_bank_count != 8 && g_ip->nuca_bank_count != 16 &&
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g_ip->nuca_bank_count != 32 && g_ip->nuca_bank_count != 64) {
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fprintf(stderr,"Incorrect bank count value! Please fix the value in cache.cfg\n");
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}
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bank_start = (int)logtwo((double)g_ip->nuca_bank_count);
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iterations = bank_start+1;
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g_ip->cache_sz = g_ip->cache_sz/g_ip->nuca_bank_count;
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}
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cout << "Simulating various NUCA configurations\n";
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for (it=bank_start; it<iterations; it++) { /* different bank count values */
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ures.tag_array2 = &tag;
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ures.data_array2 = &data;
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/*
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* find the optimal bank organization
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*/
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solve(&ures);
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// output_UCA(&ures);
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bank_count = g_ip->nuca_cache_sz/g_ip->cache_sz;
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cout << "====" << g_ip->cache_sz << "\n";
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for (wr=wt_min; wr<=wt_max; wr++) {
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for (ro=0; ro<ROUTER_TYPES; ro++)
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{
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flit_width = (int) router_s[ro]->flit_size; //initialize router
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nuca_list.back()->nuca_pda.cycle_time = router_s[ro]->cycle_time;
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/* calculate router and wire parameters */
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double vlength = ures.cache_ht; /* length of the wire (u)*/
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double hlength = ures.cache_len; // u
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/* find delay, area, and power for wires */
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wire_vertical[wr] = new Wire((enum Wire_type) wr, vlength);
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wire_horizontal[wr] = new Wire((enum Wire_type) wr, hlength);
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hor_hop_lat = calc_cycles(wire_horizontal[wr]->delay,
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1/(nuca_list.back()->nuca_pda.cycle_time*.001));
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ver_hop_lat = calc_cycles(wire_vertical[wr]->delay,
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1/(nuca_list.back()->nuca_pda.cycle_time*.001));
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/*
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* assume a grid like topology and explore for optimal network
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* configuration using different row and column count values.
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*/
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for (c=1; c<=(unsigned int)bank_count; c++) {
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while (bank_count%c != 0) c++;
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r = bank_count/c;
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/*
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* to find the avg access latency of a NUCA cache, uncontended
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* access time to each bank from the
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* cache controller is calculated.
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* avg latency =
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* sum of the access latencies to individual banks)/bank
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* count value.
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*/
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totno_hops = totno_hhops = totno_vhops = tot_lat = 0;
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k = 1;
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for (i=0; i<r; i++) {
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for (j=0; j<c; j++) {
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/*
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* vertical hops including the
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* first hop from the cache controller
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*/
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curr_hop = i + 1;
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curr_hop += j; /* horizontal hops */
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totno_hhops += j;
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totno_vhops += (i+1);
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curr_acclat = (i * ver_hop_lat + CONTR_2_BANK_LAT +
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j * hor_hop_lat);
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tot_lat += curr_acclat;
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totno_hops += curr_hop;
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}
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}
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avg_lat = tot_lat/bank_count;
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avg_hop = totno_hops/bank_count;
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avg_hhop = totno_hhops/bank_count;
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avg_vhop = totno_vhops/bank_count;
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/* net access latency */
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curr_acclat = 2*avg_lat + 2*(router_s[ro]->delay*avg_hop) +
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calc_cycles(ures.access_time,
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1/(nuca_list.back()->nuca_pda.cycle_time*.001));
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/* avg access lat of nuca */
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avg_dyn_power =
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avg_hop *
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(router_s[ro]->power.readOp.dynamic) + avg_hhop *
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(wire_horizontal[wr]->power.readOp.dynamic) *
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(g_ip->block_sz*8 + 64) + avg_vhop *
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(wire_vertical[wr]->power.readOp.dynamic) *
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(g_ip->block_sz*8 + 64) + ures.power.readOp.dynamic;
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avg_leakage_power =
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bank_count * router_s[ro]->power.readOp.leakage +
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avg_hhop * (wire_horizontal[wr]->power.readOp.leakage*
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wire_horizontal[wr]->delay) * flit_width +
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avg_vhop * (wire_vertical[wr]->power.readOp.leakage *
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wire_horizontal[wr]->delay);
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if (curr_acclat < opt_acclat) {
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opt_acclat = curr_acclat;
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opt_tot_lat = tot_lat;
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opt_avg_lat = avg_lat;
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opt_totno_hops = totno_hops;
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opt_avg_hop = avg_hop;
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opt_rows = r;
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opt_columns = c;
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opt_dyn_power = avg_dyn_power;
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opt_leakage_power = avg_leakage_power;
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}
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totno_hops = 0;
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tot_lat = 0;
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totno_hhops = 0;
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totno_vhops = 0;
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}
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nuca_list.back()->wire_pda.power.readOp.dynamic =
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opt_avg_hop * flit_width *
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(wire_horizontal[wr]->power.readOp.dynamic +
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wire_vertical[wr]->power.readOp.dynamic);
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nuca_list.back()->avg_hops = opt_avg_hop;
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/* network delay/power */
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nuca_list.back()->h_wire = wire_horizontal[wr];
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nuca_list.back()->v_wire = wire_vertical[wr];
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nuca_list.back()->router = router_s[ro];
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/* bank delay/power */
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nuca_list.back()->bank_pda.delay = ures.access_time;
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nuca_list.back()->bank_pda.power = ures.power;
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nuca_list.back()->bank_pda.area.h = ures.cache_ht;
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nuca_list.back()->bank_pda.area.w = ures.cache_len;
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nuca_list.back()->bank_pda.cycle_time = ures.cycle_time;
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num_cyc = calc_cycles(nuca_list.back()->bank_pda.delay /*s*/,
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1/(nuca_list.back()->nuca_pda.cycle_time*.001/*GHz*/));
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if(num_cyc%2 != 0) num_cyc++;
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if (num_cyc > 16) num_cyc = 16; // we have data only up to 16 cycles
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if (it < 7) {
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nuca_list.back()->nuca_pda.delay = opt_acclat +
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cont_stats[l2_c][core_in][ro][it][num_cyc/2-1];
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nuca_list.back()->contention =
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cont_stats[l2_c][core_in][ro][it][num_cyc/2-1];
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}
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else {
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nuca_list.back()->nuca_pda.delay = opt_acclat +
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cont_stats[l2_c][core_in][ro][7][num_cyc/2-1];
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nuca_list.back()->contention =
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cont_stats[l2_c][core_in][ro][7][num_cyc/2-1];
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}
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nuca_list.back()->nuca_pda.power.readOp.dynamic = opt_dyn_power;
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nuca_list.back()->nuca_pda.power.readOp.leakage = opt_leakage_power;
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/* array organization */
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nuca_list.back()->bank_count = bank_count;
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nuca_list.back()->rows = opt_rows;
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nuca_list.back()->columns = opt_columns;
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calculate_nuca_area (nuca_list.back());
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minval.update_min_values(nuca_list.back());
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nuca_list.push_back(new nuca_org_t());
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opt_acclat = BIGNUM;
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}
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}
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g_ip->cache_sz /= 2;
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}
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delete(nuca_list.back());
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nuca_list.pop_back();
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opt_n = find_optimal_nuca(&nuca_list, &minval);
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print_nuca(opt_n);
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g_ip->cache_sz = g_ip->nuca_cache_sz/opt_n->bank_count;
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list<nuca_org_t *>::iterator niter;
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for (niter = nuca_list.begin(); niter != nuca_list.end(); ++niter)
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{
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delete *niter;
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}
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nuca_list.clear();
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for(int i=0; i < ROUTER_TYPES; i++)
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{
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delete router_s[i];
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}
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g_ip->display_ip();
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// g_ip->force_cache_config = true;
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// g_ip->ndwl = 8;
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// g_ip->ndbl = 16;
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// g_ip->nspd = 4;
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// g_ip->ndcm = 1;
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// g_ip->ndsam1 = 8;
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// g_ip->ndsam2 = 32;
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}
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void
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Nuca::print_nuca (nuca_org_t *fr)
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{
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printf("\n---------- CACTI version 6.5, Non-uniform Cache Access "
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"----------\n\n");
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printf("Optimal number of banks - %d\n", fr->bank_count);
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printf("Grid organization rows x columns - %d x %d\n",
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fr->rows, fr->columns);
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printf("Network frequency - %g GHz\n",
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(1/fr->nuca_pda.cycle_time)*1e3);
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printf("Cache dimension (mm x mm) - %g x %g\n",
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fr->nuca_pda.area.h,
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fr->nuca_pda.area.w);
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fr->router->print_router();
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printf("\n\nWire stats:\n");
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if (fr->h_wire->wt == Global) {
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printf("\tWire type - Full swing global wires with least "
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"possible delay\n");
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}
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else if (fr->h_wire->wt == Global_5) {
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printf("\tWire type - Full swing global wires with "
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"5%% delay penalty\n");
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}
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else if (fr->h_wire->wt == Global_10) {
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printf("\tWire type - Full swing global wires with "
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"10%% delay penalty\n");
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}
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else if (fr->h_wire->wt == Global_20) {
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printf("\tWire type - Full swing global wires with "
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"20%% delay penalty\n");
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}
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else if (fr->h_wire->wt == Global_30) {
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printf("\tWire type - Full swing global wires with "
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"30%% delay penalty\n");
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}
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else if(fr->h_wire->wt == Low_swing) {
|
|
printf("\tWire type - Low swing wires\n");
|
|
}
|
|
|
|
printf("\tHorizontal link delay - %g (ns)\n",
|
|
fr->h_wire->delay*1e9);
|
|
printf("\tVertical link delay - %g (ns)\n",
|
|
fr->v_wire->delay*1e9);
|
|
printf("\tDelay/length - %g (ns/mm)\n",
|
|
fr->h_wire->delay*1e9/fr->bank_pda.area.w);
|
|
printf("\tHorizontal link energy -dynamic/access %g (nJ)\n"
|
|
"\t -leakage %g (nW)\n\n",
|
|
fr->h_wire->power.readOp.dynamic*1e9,
|
|
fr->h_wire->power.readOp.leakage*1e9);
|
|
printf("\tVertical link energy -dynamic/access %g (nJ)\n"
|
|
"\t -leakage %g (nW)\n\n",
|
|
fr->v_wire->power.readOp.dynamic*1e9,
|
|
fr->v_wire->power.readOp.leakage*1e9);
|
|
printf("\n\n");
|
|
fr->v_wire->print_wire();
|
|
printf("\n\nBank stats:\n");
|
|
}
|
|
|
|
|
|
nuca_org_t *
|
|
Nuca::find_optimal_nuca (list<nuca_org_t *> *n, min_values_t *minval)
|
|
{
|
|
double cost = 0;
|
|
double min_cost = BIGNUM;
|
|
nuca_org_t *res = NULL;
|
|
float d, a, dp, lp, c;
|
|
int v;
|
|
dp = g_ip->dynamic_power_wt_nuca;
|
|
lp = g_ip->leakage_power_wt_nuca;
|
|
a = g_ip->area_wt_nuca;
|
|
d = g_ip->delay_wt_nuca;
|
|
c = g_ip->cycle_time_wt_nuca;
|
|
|
|
list<nuca_org_t *>::iterator niter;
|
|
|
|
|
|
for (niter = n->begin(); niter != n->end(); niter++) {
|
|
fprintf(stderr, "\n-----------------------------"
|
|
"---------------\n");
|
|
|
|
|
|
printf("NUCA___stats %d \tbankcount: lat = %g \tdynP = %g \twt = %d\t "
|
|
"bank_dpower = %g \tleak = %g \tcycle = %g\n",
|
|
(*niter)->bank_count,
|
|
(*niter)->nuca_pda.delay,
|
|
(*niter)->nuca_pda.power.readOp.dynamic,
|
|
(*niter)->h_wire->wt,
|
|
(*niter)->bank_pda.power.readOp.dynamic,
|
|
(*niter)->nuca_pda.power.readOp.leakage,
|
|
(*niter)->nuca_pda.cycle_time);
|
|
|
|
|
|
if (g_ip->ed == 1) {
|
|
cost = ((*niter)->nuca_pda.delay/minval->min_delay)*
|
|
((*niter)->nuca_pda.power.readOp.dynamic/minval->min_dyn);
|
|
if (min_cost > cost) {
|
|
min_cost = cost;
|
|
res = ((*niter));
|
|
}
|
|
}
|
|
else if (g_ip->ed == 2) {
|
|
cost = ((*niter)->nuca_pda.delay/minval->min_delay)*
|
|
((*niter)->nuca_pda.delay/minval->min_delay)*
|
|
((*niter)->nuca_pda.power.readOp.dynamic/minval->min_dyn);
|
|
if (min_cost > cost) {
|
|
min_cost = cost;
|
|
res = ((*niter));
|
|
}
|
|
}
|
|
else {
|
|
/*
|
|
* check whether the current organization
|
|
* meets the input deviation constraints
|
|
*/
|
|
v = check_nuca_org((*niter), minval);
|
|
if (minval->min_leakage == 0) minval->min_leakage = 0.1; //FIXME remove this after leakage modeling
|
|
|
|
if (v) {
|
|
cost = (d * ((*niter)->nuca_pda.delay/minval->min_delay) +
|
|
c * ((*niter)->nuca_pda.cycle_time/minval->min_cyc) +
|
|
dp * ((*niter)->nuca_pda.power.readOp.dynamic/minval->min_dyn) +
|
|
lp * ((*niter)->nuca_pda.power.readOp.leakage/minval->min_leakage) +
|
|
a * ((*niter)->nuca_pda.area.get_area()/minval->min_area));
|
|
fprintf(stderr, "cost = %g\n", cost);
|
|
|
|
if (min_cost > cost) {
|
|
min_cost = cost;
|
|
res = ((*niter));
|
|
}
|
|
}
|
|
else {
|
|
niter = n->erase(niter);
|
|
if (niter !=n->begin())
|
|
niter --;
|
|
}
|
|
}
|
|
}
|
|
return res;
|
|
}
|
|
|
|
int
|
|
Nuca::check_nuca_org (nuca_org_t *n, min_values_t *minval)
|
|
{
|
|
if (((n->nuca_pda.delay - minval->min_delay)*100/minval->min_delay) > g_ip->delay_dev_nuca) {
|
|
return 0;
|
|
}
|
|
if (((n->nuca_pda.power.readOp.dynamic - minval->min_dyn)/minval->min_dyn)*100 >
|
|
g_ip->dynamic_power_dev_nuca) {
|
|
return 0;
|
|
}
|
|
if (((n->nuca_pda.power.readOp.leakage - minval->min_leakage)/minval->min_leakage)*100 >
|
|
g_ip->leakage_power_dev_nuca) {
|
|
return 0;
|
|
}
|
|
if (((n->nuca_pda.cycle_time - minval->min_cyc)/minval->min_cyc)*100 >
|
|
g_ip->cycle_time_dev_nuca) {
|
|
return 0;
|
|
}
|
|
if (((n->nuca_pda.area.get_area() - minval->min_area)/minval->min_area)*100 >
|
|
g_ip->area_dev_nuca) {
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
void
|
|
Nuca::calculate_nuca_area (nuca_org_t *nuca)
|
|
{
|
|
nuca->nuca_pda.area.h=
|
|
nuca->rows * ((nuca->h_wire->wire_width +
|
|
nuca->h_wire->wire_spacing)
|
|
* nuca->router->flit_size +
|
|
nuca->bank_pda.area.h);
|
|
|
|
nuca->nuca_pda.area.w =
|
|
nuca->columns * ((nuca->v_wire->wire_width +
|
|
nuca->v_wire->wire_spacing)
|
|
* nuca->router->flit_size +
|
|
nuca->bank_pda.area.w);
|
|
}
|
|
|