gem5/src/arch/x86/isa
Gabe Black e524240d68 Make disassembled x86 register indices reflect their size.
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.

--HG--
extra : convert_revision : d495ac4f5756dc55a5f71953ff6963b3c030e6cb
2007-07-17 18:12:33 -07:00
..
decoder Implemented jnz. 2007-07-17 16:55:33 -07:00
formats Pull some hard coded base classes out of the isa description. 2007-07-14 17:14:19 -07:00
insts Implemented jnz. 2007-07-17 16:55:33 -07:00
microops Make disassembled x86 register indices reflect their size. 2007-07-17 18:12:33 -07:00
bitfields.isa Add a stack size bitfield and expose the mode component of the ExtMachInst. 2007-06-19 14:15:21 +00:00
includes.isa Actually include miscregs.hh 2007-07-17 13:30:23 -07:00
macroop.isa Make memory instructions work better, add more macroop implementations, add an lea microop, move EmulEnv into it's own .cc and .hh. 2007-06-20 15:02:50 +00:00
main.isa Pull some hard coded base classes out of the isa description. 2007-07-14 17:14:19 -07:00
microasm.isa Add symbols for each of the flags a microop could set and each condition it could check. 2007-07-17 15:27:28 -07:00
operands.isa Add in operand which holds the condition code bits of the flag register. 2007-07-17 15:28:48 -07:00
outputblock.isa Pull some hard coded base classes out of the isa description. 2007-07-14 17:14:19 -07:00
specialize.isa Implement rip relative addressing and put in some missing loads and stores. 2007-06-20 19:08:04 +00:00