a4ed65d0fa
Debug FP instructions to handle these FP insts
arch/mips/isa/bitfields.isa:
add Bitfield for Floating Point Condition Codes
arch/mips/isa/decoder.isa:
Follow instruction naming style with FP single insts
Send the float value to the convert&round functions in single FP
add ll inst support
add 'token' sc support
arch/mips/isa_traits.cc:
Add SINGLE->WORD, WORD->SINGLE, & WORD->DOUBLE conversions
arch/mips/regfile.hh:
update header files
arch/mips/regfile/float_regfile.hh:
Add more FP registers
--HG--
rename : arch/mips/int_regfile.hh => arch/mips/regfile/int_regfile.hh
rename : arch/mips/misc_regfile.hh => arch/mips/regfile/misc_regfile.hh
extra : convert_revision : 92faf0bfd8542ade762ac569ec158d198f6a9c7e
96 lines
3.2 KiB
C++
96 lines
3.2 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_MIPS_MISC_REGFILE_HH__
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#define __ARCH_MIPS_MISC_REGFILE_HH__
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#include "arch/mips/types.hh"
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#include "arch/mips/constants.hh"
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#include "sim/faults.hh"
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class Checkpoint;
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class ExecContext;
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class Regfile;
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namespace MipsISA
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{
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class MiscRegFile {
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protected:
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uint64_t fpcr; // floating point condition codes
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uint64_t uniq; // process-unique register
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bool lock_flag; // lock flag for LL/SC
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Addr lock_addr; // lock address for LL/SC
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MiscReg miscRegFile[NumMiscRegs];
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public:
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//These functions should be removed once the simplescalar cpu model
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//has been replaced.
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int getInstAsid();
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int getDataAsid();
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void copyMiscRegs(ExecContext *xc);
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MiscReg readReg(int misc_reg)
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{
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return miscRegFile[misc_reg];
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}
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MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
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{
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return miscRegFile[misc_reg];
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}
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Fault setReg(int misc_reg, const MiscReg &val)
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{
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miscRegFile[misc_reg] = val; return NoFault;
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}
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Fault setRegWithEffect(int misc_reg, const MiscReg &val,
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ExecContext *xc)
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{
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miscRegFile[misc_reg] = val; return NoFault;
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}
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#if FULL_SYSTEM
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void clearIprs() { }
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protected:
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InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
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private:
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MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
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Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
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#endif
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friend class RegFile;
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};
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} // namespace MipsISA
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#endif
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