441 lines
47 KiB
Text
441 lines
47 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 183932235 # Number of BTB hits
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global.BPredUnit.BTBLookups 208089812 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 84447535 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 256528366 # Number of conditional branches predicted
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global.BPredUnit.lookups 256528366 # Number of BP lookups
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global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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host_inst_rate 94020 # Simulator instruction rate (inst/s)
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host_mem_usage 184848 # Number of bytes of host memory used
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host_seconds 14950.16 # Real time elapsed on the host
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host_tick_rate 73409017 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 458856790 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 141228058 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 745627925 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 302069201 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1405610550 # Number of instructions simulated
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sim_seconds 1.097477 # Number of seconds simulated
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sim_ticks 1097476890500 # Number of ticks simulated
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system.cpu.commit.COM:branches 86246390 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 9005633 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 1955398373
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 1080294174 5524.68%
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1 576226777 2946.85%
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2 118746551 607.28%
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3 121516054 621.44%
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4 26673737 136.41%
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5 9328411 47.71%
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6 9370387 47.92%
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7 4236649 21.67%
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8 9005633 46.06%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 1489528973 # Number of instructions committed
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system.cpu.commit.COM:loads 402516086 # Number of loads committed
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system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
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system.cpu.commit.COM:refs 569373868 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 84447535 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 1399558822 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1405610550 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated
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system.cpu.cpi 1.561566 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.561566 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 422711094 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 22402.386533 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4523.374198 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 422473888 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5313980500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 237206 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 708416 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1072971500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 237206 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 7025 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5025 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 281000 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 201000 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 165053813 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 45668.908621 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.368381 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 164707389 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 15820806000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 346424 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1802643 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2049572000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 346424 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 1145.843040 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 587764907 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 36212.645854 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 587181277 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 21134786500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000993 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 583630 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2511059 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 3122543500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000993 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 583630 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 587764907 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 36212.645854 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 587181277 # number of overall hits
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system.cpu.dcache.overall_miss_latency 21134786500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000993 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 583630 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2511059 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 3122543500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000993 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 583630 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 508412 # number of replacements
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system.cpu.dcache.sampled_refs 512508 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.762102 # Cycle average of tags in use
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system.cpu.dcache.total_refs 587253725 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 80526000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 343259 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 406688141 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:DecodedInsts 3452580675 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 760521931 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 785512506 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 239555254 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:UnblockCycles 2675795 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 256528366 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 355016142 # Number of cache lines fetched
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system.cpu.fetch.Cycles 1201036760 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 10894008 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 3738352844 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 89458561 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.116872 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 355016142 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 183932235 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.703158 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 2194953627
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system.cpu.fetch.rateDist.min_value 0
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0 1348933053 6145.61%
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1 256313247 1167.74%
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2 82698191 376.77%
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3 38326183 174.61%
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4 84519360 385.06%
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5 41105906 187.27%
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6 32923583 150.00%
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7 20556634 93.65%
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8 289577470 1319.29%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 355016079 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 7452.363368 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 5292.836041 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 355014725 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 10090500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 7166500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 262196.990399 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 355016079 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 7452.363368 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency
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system.cpu.icache.demand_hits 355014725 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 10090500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
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system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 7166500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 355016079 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 7452.363368 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 355014725 # number of overall hits
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system.cpu.icache.overall_miss_latency 10090500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
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system.cpu.icache.overall_misses 1354 # number of overall misses
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system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 7166500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 208 # number of replacements
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system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1042.348080 # Cycle average of tags in use
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system.cpu.icache.total_refs 355014725 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 94965 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 128778452 # Number of branches executed
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system.cpu.iew.EXEC:nop 354384689 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.865881 # Inst execution rate
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system.cpu.iew.EXEC:refs 753461994 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 210026063 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 1497813793 # num instructions consuming a value
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system.cpu.iew.WB:count 1867109874 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.963032 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 1442442170 # num instructions producing a value
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system.cpu.iew.WB:rate 0.850638 # insts written-back per cycle
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system.cpu.iew.WB:sent 1877161076 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 91327681 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 454443 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 745627925 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 21367021 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 17089542 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 302069201 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 2889153048 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 543435931 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 103575555 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 1900567912 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 61243 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 9772 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 239555254 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 95884 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 119997179 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 80650 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 5250080 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 343111839 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 135211419 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 5250080 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 1516982 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 89810699 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.640383 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.640383 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 2004143467 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 0 0.00% # Type of FU issued
|
|
IntAlu 1186366605 59.20% # Type of FU issued
|
|
IntMult 0 0.00% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 3003253 0.15% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 584611723 29.17% # Type of FU issued
|
|
MemWrite 230161886 11.48% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 6010355 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.002999 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 143340 2.38% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 241345 4.02% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 5244225 87.25% # attempts to use FU when none available
|
|
MemWrite 381445 6.35% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 2194953627
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 1076765226 4905.64%
|
|
1 582878371 2655.54%
|
|
2 298125643 1358.23%
|
|
3 159003575 724.41%
|
|
4 52530250 239.32%
|
|
5 16707223 76.12%
|
|
6 8404252 38.29%
|
|
7 392238 1.79%
|
|
8 146849 0.67%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 0.913069 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 2513084593 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 2004143467 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 21683766 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 1087893079 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 3817087 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 19440265 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 1299740082 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadExReq_accesses 275303 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 4888.651776 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2888.651776 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1345860500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 275303 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 795254500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 275303 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 238559 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4206.099871 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2206.099871 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 56424 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 766078000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.763480 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 182135 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 401808000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.763480 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 182135 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 71169 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4205.419494 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2205.419494 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 299295500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 71169 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 156957500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 71169 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 343259 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
|
|
system.cpu.l2cache.Writeback_misses 343259 # number of Writeback misses
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
|
|
system.cpu.l2cache.Writeback_mshr_misses 343259 # number of Writeback MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 4.652891 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 513862 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 4616.884693 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 56424 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 2111938500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.890196 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 457438 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 1197062500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.890196 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 457438 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 513862 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 4616.884693 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 56424 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 2111938500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.890196 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 457438 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 1197062500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.890196 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 457438 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 19390 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 20786 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 8527.413561 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 96715 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 2194953627 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 13000888 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:FullRegisterEvents 9 # Number of times there has been no free registers
|
|
system.cpu.rename.RENAME:IQFullEvents 47407 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 822770114 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 20101500 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 4935577703 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 3109070263 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 2428488542 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 723045080 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 239555254 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 28402170 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 1183717485 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 368180121 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 21968418 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 159248004 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 21723083 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|