This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen!
167 lines
6.1 KiB
C++
167 lines
6.1 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/resources/resource_list.hh"
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using namespace std;
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namespace ThePipeline {
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//@TODO: create my own Instruction Schedule Class
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//that operates as a Priority QUEUE
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int getNextPriority(DynInstPtr &inst, int stage_num)
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{
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int cur_pri = 20;
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/*
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std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
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entryCompare>::iterator sked_it = inst->resSched.begin();
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std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
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entryCompare>::iterator sked_end = inst->resSched.end();
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while (sked_it != sked_end) {
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if (sked_it.top()->stageNum == stage_num) {
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cur_pri = sked_it.top()->priority;
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}
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sked_it++;
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}
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*/
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return cur_pri;
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}
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void createFrontEndSchedule(DynInstPtr &inst)
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{
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int stNum = 0;
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int stPri = 0;
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// Get Pointer to Instuction's Schedule
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ResSchedule *inst_sched = &inst->resSched;
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//
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// IF - Stage 0
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// ---------------------------------------
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inst_sched->push(new ScheduleEntry(stNum, stPri++, FetchSeq, FetchSeqUnit::AssignNextPC));
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inst_sched->push(new ScheduleEntry(stNum, stPri++, ITLB, TLBUnit::FetchLookup));
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inst_sched->push(new ScheduleEntry(stNum, stPri++, ICache, CacheUnit::InitiateFetch));
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//
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// DE - Stage 1
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// ---------------------------------------
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stNum++; stPri = 0;
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inst_sched->push(new ScheduleEntry(stNum, stPri++, ICache, CacheUnit::CompleteFetch));
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inst_sched->push(new ScheduleEntry(stNum, stPri++, Decode, DecodeUnit::DecodeInst));
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inst_sched->push(new ScheduleEntry(stNum, stPri++, BPred, BranchPredictor::PredictBranch));
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inst_sched->push(new ScheduleEntry(stNum, stPri++, FetchSeq, FetchSeqUnit::UpdateTargetPC));
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}
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bool createBackEndSchedule(DynInstPtr &inst)
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{
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if (!inst->staticInst) {
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return false;
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}
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int stNum = BackEndStartStage;
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int stPri = 0;
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// Get Pointer to Instuction's Schedule
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ResSchedule *inst_sched = &inst->resSched;
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//
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// EX - Stage 2
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// ---------------------------------------
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for (int idx=0; idx < inst->numSrcRegs(); idx++) {
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if (!idx || !inst->isStore())
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inst_sched->push(new ScheduleEntry(stNum, stPri++, RegManager, UseDefUnit::ReadSrcReg, idx));
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}
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if ( inst->isNonSpeculative() ) {
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// skip execution of non speculative insts until later
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} else if (inst->isMemRef()) {
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inst_sched->push(new ScheduleEntry(stNum, stPri++, AGEN, AGENUnit::GenerateAddr));
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if ( inst->isLoad() ) {
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inst_sched->push(new ScheduleEntry(stNum, stPri++, DTLB, TLBUnit::DataLookup));
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inst_sched->push(new ScheduleEntry(stNum, stPri++, DCache, CacheUnit::InitiateReadData));
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}
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} else {
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inst_sched->push(new ScheduleEntry(stNum, stPri++, ExecUnit, ExecutionUnit::ExecuteInst));
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}
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//
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// MEM - Stage 3
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// ---------------------------------------
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stPri = 0; stNum++;
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if ( inst->isStore() ) { // for store, need src reg at this point
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inst_sched->push(new ScheduleEntry(stNum, stPri++, RegManager, UseDefUnit::ReadSrcReg, 1));
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}
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if ( inst->isLoad() ) {
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inst_sched->push(new ScheduleEntry(stNum, stPri++, DCache, CacheUnit::CompleteReadData));
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} else if ( inst->isStore() ) {
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inst_sched->push(new ScheduleEntry(stNum, stPri++, DTLB, TLBUnit::DataLookup));
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inst_sched->push(new ScheduleEntry(stNum, stPri++, DCache, CacheUnit::InitiateWriteData));
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}
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//
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// WB - Stage 4
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// ---------------------------------------
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stPri = 0; stNum++;
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if (inst->isNonSpeculative()) {
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if (inst->isMemRef())
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fatal("Schedule doesnt handle Non-Speculative Memory Instructions.\n");
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if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
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inst_sched->push(new ScheduleEntry(stNum, stPri++, MDU, MultDivUnit::MultDiv));
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} else {
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inst_sched->push(new ScheduleEntry(stNum, stPri++, ExecUnit, ExecutionUnit::ExecuteInst));
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}
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}
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if ( inst->isStore() )
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inst_sched->push(new ScheduleEntry(stNum, stPri++, DCache, CacheUnit::CompleteWriteData));
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// Write Back to Register File
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for (int idx=0; idx < inst->numDestRegs(); idx++) {
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inst_sched->push(new ScheduleEntry(stNum, stPri++, RegManager, UseDefUnit::WriteDestReg, idx));
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}
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// Graduate Instructions
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inst_sched->push(new ScheduleEntry(stNum, stPri++, Grad, GraduationUnit::GraduateInst));
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return true;
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}
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};
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