606 lines
66 KiB
Text
606 lines
66 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 4288852 # Simulator instruction rate (inst/s)
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host_mem_usage 294988 # Number of bytes of host memory used
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host_seconds 14.73 # Real time elapsed on the host
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host_tick_rate 127013871331 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 63154034 # Number of instructions simulated
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sim_seconds 1.870336 # Number of seconds simulated
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sim_ticks 1870335522500 # Number of ticks simulated
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system.cpu0.dcache.LoadLockedReq_accesses 188297 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_hits 172138 # number of LoadLockedReq hits
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system.cpu0.dcache.LoadLockedReq_miss_rate 0.085817 # miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_misses 16159 # number of LoadLockedReq misses
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system.cpu0.dcache.ReadReq_accesses 8981669 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_hits 7298106 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_rate 0.187444 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_misses 1683563 # number of ReadReq misses
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system.cpu0.dcache.StoreCondReq_accesses 187338 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_hits 159838 # number of StoreCondReq hits
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system.cpu0.dcache.StoreCondReq_miss_rate 0.146793 # miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_misses 27500 # number of StoreCondReq misses
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system.cpu0.dcache.WriteReq_accesses 5748261 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_hits 5374453 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_rate 0.065030 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_misses 373808 # number of WriteReq misses
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks.
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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.demand_accesses 14729930 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.cpu0.dcache.demand_hits 12672559 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_rate 0.139673 # miss rate for demand accesses
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system.cpu0.dcache.demand_misses 2057371 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.overall_accesses 14729930 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_hits 12672559 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_rate 0.139673 # miss rate for overall accesses
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system.cpu0.dcache.overall_misses 2057371 # number of overall misses
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system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.replacements 1978962 # number of replacements
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system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks.
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system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.writebacks 396793 # number of writebacks
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system.cpu0.dtb.data_accesses 698037 # DTB accesses
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system.cpu0.dtb.data_acv 251 # DTB access violations
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system.cpu0.dtb.data_hits 15091429 # DTB hits
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system.cpu0.dtb.data_misses 7805 # DTB misses
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system.cpu0.dtb.fetch_accesses 0 # ITB accesses
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system.cpu0.dtb.fetch_acv 0 # ITB acv
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system.cpu0.dtb.fetch_hits 0 # ITB hits
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system.cpu0.dtb.fetch_misses 0 # ITB misses
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system.cpu0.dtb.read_accesses 508987 # DTB read accesses
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system.cpu0.dtb.read_acv 152 # DTB read access violations
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system.cpu0.dtb.read_hits 9154530 # DTB read hits
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system.cpu0.dtb.read_misses 7079 # DTB read misses
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system.cpu0.dtb.write_accesses 189050 # DTB write accesses
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system.cpu0.dtb.write_acv 99 # DTB write access violations
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system.cpu0.dtb.write_hits 5936899 # DTB write hits
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system.cpu0.dtb.write_misses 726 # DTB write misses
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system.cpu0.icache.ReadReq_accesses 57230132 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_hits 56345132 # number of ReadReq hits
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system.cpu0.icache.ReadReq_miss_rate 0.015464 # miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_misses 885000 # number of ReadReq misses
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system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks.
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.demand_accesses 57230132 # number of demand (read+write) accesses
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system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.cpu0.icache.demand_hits 56345132 # number of demand (read+write) hits
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system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_rate 0.015464 # miss rate for demand accesses
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system.cpu0.icache.demand_misses 885000 # number of demand (read+write) misses
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system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.overall_accesses 57230132 # number of overall (read+write) accesses
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system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.icache.overall_hits 56345132 # number of overall hits
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system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
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system.cpu0.icache.overall_miss_rate 0.015464 # miss rate for overall accesses
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system.cpu0.icache.overall_misses 885000 # number of overall misses
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system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
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system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
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system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.icache.replacements 884404 # number of replacements
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system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks.
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system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use
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system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks.
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system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.writebacks 0 # number of writebacks
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system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles
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system.cpu0.itb.data_accesses 0 # DTB accesses
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system.cpu0.itb.data_acv 0 # DTB access violations
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system.cpu0.itb.data_hits 0 # DTB hits
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system.cpu0.itb.data_misses 0 # DTB misses
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system.cpu0.itb.fetch_accesses 3859041 # ITB accesses
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system.cpu0.itb.fetch_acv 127 # ITB acv
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system.cpu0.itb.fetch_hits 3855556 # ITB hits
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system.cpu0.itb.fetch_misses 3485 # ITB misses
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system.cpu0.itb.read_accesses 0 # DTB read accesses
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system.cpu0.itb.read_acv 0 # DTB read access violations
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system.cpu0.itb.read_hits 0 # DTB read hits
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system.cpu0.itb.read_misses 0 # DTB read misses
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system.cpu0.itb.write_accesses 0 # DTB write accesses
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system.cpu0.itb.write_acv 0 # DTB write access violations
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system.cpu0.itb.write_hits 0 # DTB write hits
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system.cpu0.itb.write_misses 0 # DTB write misses
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system.cpu0.kern.callpal::cserve 1 0.00% # number of callpals executed
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system.cpu0.kern.callpal::wripir 110 0.06% # number of callpals executed
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system.cpu0.kern.callpal::wrmces 1 0.00% # number of callpals executed
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system.cpu0.kern.callpal::wrfen 1 0.00% # number of callpals executed
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system.cpu0.kern.callpal::wrvptptr 1 0.00% # number of callpals executed
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system.cpu0.kern.callpal::swpctx 3762 2.05% # number of callpals executed
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system.cpu0.kern.callpal::tbi 38 0.02% # number of callpals executed
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system.cpu0.kern.callpal::wrent 7 0.00% # number of callpals executed
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system.cpu0.kern.callpal::swpipl 168035 91.68% # number of callpals executed
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system.cpu0.kern.callpal::rdps 6150 3.36% # number of callpals executed
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system.cpu0.kern.callpal::wrkgp 1 0.00% # number of callpals executed
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system.cpu0.kern.callpal::wrusp 3 0.00% # number of callpals executed
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system.cpu0.kern.callpal::rdusp 7 0.00% # number of callpals executed
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system.cpu0.kern.callpal::whami 2 0.00% # number of callpals executed
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system.cpu0.kern.callpal::rti 4673 2.55% # number of callpals executed
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system.cpu0.kern.callpal::callsys 357 0.19% # number of callpals executed
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system.cpu0.kern.callpal::imb 142 0.08% # number of callpals executed
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system.cpu0.kern.callpal::total 183291 # number of callpals executed
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed
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system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
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system.cpu0.kern.ipl_count::0 71004 40.60% # number of times we switched to this ipl
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system.cpu0.kern.ipl_count::21 243 0.14% # number of times we switched to this ipl
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system.cpu0.kern.ipl_count::22 1908 1.09% # number of times we switched to this ipl
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system.cpu0.kern.ipl_count::30 8 0.00% # number of times we switched to this ipl
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system.cpu0.kern.ipl_count::31 101705 58.16% # number of times we switched to this ipl
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system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl
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system.cpu0.kern.ipl_good::0 69637 49.24% # number of times we switched to this ipl from a different ipl
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system.cpu0.kern.ipl_good::21 243 0.17% # number of times we switched to this ipl from a different ipl
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system.cpu0.kern.ipl_good::22 1908 1.35% # number of times we switched to this ipl from a different ipl
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system.cpu0.kern.ipl_good::30 8 0.01% # number of times we switched to this ipl from a different ipl
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system.cpu0.kern.ipl_good::31 69629 49.23% # number of times we switched to this ipl from a different ipl
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system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl
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system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_ticks::21 20110000 0.00% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_ticks::22 82044000 0.00% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_ticks::30 949500 0.00% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_ticks::31 17242445000 0.92% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.mode_good::kernel 1157
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system.cpu0.kern.mode_good::user 1158
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system.cpu0.kern.mode_good::idle 0
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system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches
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system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches
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system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
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system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches
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system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
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system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
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system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::user 957009000 0.05% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% # number of ticks spent at the given mode
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system.cpu0.kern.swap_context 3763 # number of times the context was actually changed
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system.cpu0.kern.syscall::2 6 2.65% # number of syscalls executed
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system.cpu0.kern.syscall::3 19 8.41% # number of syscalls executed
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system.cpu0.kern.syscall::4 2 0.88% # number of syscalls executed
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system.cpu0.kern.syscall::6 32 14.16% # number of syscalls executed
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system.cpu0.kern.syscall::12 1 0.44% # number of syscalls executed
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system.cpu0.kern.syscall::15 1 0.44% # number of syscalls executed
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system.cpu0.kern.syscall::17 9 3.98% # number of syscalls executed
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system.cpu0.kern.syscall::19 8 3.54% # number of syscalls executed
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system.cpu0.kern.syscall::20 6 2.65% # number of syscalls executed
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system.cpu0.kern.syscall::23 2 0.88% # number of syscalls executed
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system.cpu0.kern.syscall::24 4 1.77% # number of syscalls executed
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system.cpu0.kern.syscall::33 7 3.10% # number of syscalls executed
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system.cpu0.kern.syscall::41 2 0.88% # number of syscalls executed
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system.cpu0.kern.syscall::45 37 16.37% # number of syscalls executed
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system.cpu0.kern.syscall::47 4 1.77% # number of syscalls executed
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system.cpu0.kern.syscall::48 8 3.54% # number of syscalls executed
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system.cpu0.kern.syscall::54 10 4.42% # number of syscalls executed
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system.cpu0.kern.syscall::58 1 0.44% # number of syscalls executed
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system.cpu0.kern.syscall::59 4 1.77% # number of syscalls executed
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system.cpu0.kern.syscall::71 30 13.27% # number of syscalls executed
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system.cpu0.kern.syscall::73 3 1.33% # number of syscalls executed
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system.cpu0.kern.syscall::74 8 3.54% # number of syscalls executed
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system.cpu0.kern.syscall::87 1 0.44% # number of syscalls executed
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system.cpu0.kern.syscall::90 2 0.88% # number of syscalls executed
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system.cpu0.kern.syscall::92 9 3.98% # number of syscalls executed
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system.cpu0.kern.syscall::97 2 0.88% # number of syscalls executed
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system.cpu0.kern.syscall::98 2 0.88% # number of syscalls executed
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system.cpu0.kern.syscall::132 2 0.88% # number of syscalls executed
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system.cpu0.kern.syscall::144 2 0.88% # number of syscalls executed
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system.cpu0.kern.syscall::147 2 0.88% # number of syscalls executed
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system.cpu0.kern.syscall::total 226 # number of syscalls executed
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system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
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system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
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system.cpu0.num_insts 57222076 # Number of instructions executed
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system.cpu0.num_refs 15330887 # Number of memory references
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system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses)
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system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits
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system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses
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system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses
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system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses)
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system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits
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system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses
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system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses
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system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses)
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system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits
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system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses
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system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses
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system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses)
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system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits
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system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses
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system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses
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system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_hits 1812118 # number of overall hits
|
|
system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_misses 72152 # number of overall misses
|
|
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.replacements 62338 # number of replacements
|
|
system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.writebacks 30848 # number of writebacks
|
|
system.cpu1.dtb.data_accesses 323622 # DTB accesses
|
|
system.cpu1.dtb.data_acv 116 # DTB access violations
|
|
system.cpu1.dtb.data_hits 1914885 # DTB hits
|
|
system.cpu1.dtb.data_misses 3692 # DTB misses
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.read_accesses 220342 # DTB read accesses
|
|
system.cpu1.dtb.read_acv 58 # DTB read access violations
|
|
system.cpu1.dtb.read_hits 1163439 # DTB read hits
|
|
system.cpu1.dtb.read_misses 3277 # DTB read misses
|
|
system.cpu1.dtb.write_accesses 103280 # DTB write accesses
|
|
system.cpu1.dtb.write_acv 58 # DTB write access violations
|
|
system.cpu1.dtb.write_hits 751446 # DTB write hits
|
|
system.cpu1.dtb.write_misses 415 # DTB write misses
|
|
system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks.
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_hits 5832136 # number of overall hits
|
|
system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_misses 103630 # number of overall misses
|
|
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.icache.replacements 103091 # number of replacements
|
|
system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.writebacks 0 # number of writebacks
|
|
system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.fetch_accesses 1469938 # ITB accesses
|
|
system.cpu1.itb.fetch_acv 57 # ITB acv
|
|
system.cpu1.itb.fetch_hits 1468399 # ITB hits
|
|
system.cpu1.itb.fetch_misses 1539 # ITB misses
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.kern.callpal::cserve 1 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wripir 8 0.02% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpctx 470 1.46% # number of callpals executed
|
|
system.cpu1.kern.callpal::tbi 15 0.05% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrent 7 0.02% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpipl 26238 81.66% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdps 2576 8.02% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrusp 4 0.01% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdusp 2 0.01% # number of callpals executed
|
|
system.cpu1.kern.callpal::whami 3 0.01% # number of callpals executed
|
|
system.cpu1.kern.callpal::rti 2607 8.11% # number of callpals executed
|
|
system.cpu1.kern.callpal::callsys 158 0.49% # number of callpals executed
|
|
system.cpu1.kern.callpal::imb 38 0.12% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::total 32131 # number of callpals executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
|
|
system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
|
|
system.cpu1.kern.ipl_count::0 10328 33.46% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::22 1907 6.18% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::30 110 0.36% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::31 18518 60.00% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_good::0 10318 45.77% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::22 1907 8.46% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::30 110 0.49% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::31 10208 45.28% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::22 82001000 0.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::30 14064500 0.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::31 10905353000 0.58% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.mode_good::kernel 612
|
|
system.cpu1.kern.mode_good::user 580
|
|
system.cpu1.kern.mode_good::idle 32
|
|
system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 580 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 508289000 0.03% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 471 # number of times the context was actually changed
|
|
system.cpu1.kern.syscall::2 2 2.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::3 11 11.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::4 2 2.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::6 10 10.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::17 6 6.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::19 2 2.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::23 2 2.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::24 2 2.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::33 4 4.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::45 17 17.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::47 2 2.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::48 2 2.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::59 3 3.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::71 24 24.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::74 8 8.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::90 1 1.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::132 2 2.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::total 100 # number of syscalls executed
|
|
system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
|
|
system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
|
|
system.cpu1.num_insts 5931958 # Number of instructions executed
|
|
system.cpu1.num_refs 1926645 # Number of memory references
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_misses 175 # number of ReadReq misses
|
|
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses 41727 # number of demand (read+write) accesses
|
|
system.iocache.demand_avg_miss_latency 0 # average overall miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.demand_hits 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
|
|
system.iocache.demand_misses 41727 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.overall_accesses 41727 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency 0 # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
|
|
system.iocache.overall_misses 41727 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.replacements 41695 # number of replacements
|
|
system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 0.435437 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 41520 # number of writebacks
|
|
system.l2c.ReadExReq_accesses 306247 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses 306247 # number of ReadExReq misses
|
|
system.l2c.ReadReq_accesses 2724267 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_hits 1759731 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_rate 0.354053 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses 964536 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_accesses 125007 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses 125007 # number of UpgradeReq misses
|
|
system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits 427641 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 1.788900 # Average number of references to valid blocks.
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses 3030514 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.l2c.demand_hits 1759731 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate 0.419329 # miss rate for demand accesses
|
|
system.l2c.demand_misses 1270783 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.overall_accesses 3030514 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits 1759731 # number of overall hits
|
|
system.l2c.overall_miss_latency 0 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate 0.419329 # miss rate for overall accesses
|
|
system.l2c.overall_misses 1270783 # number of overall misses
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 1056803 # number of replacements
|
|
system.l2c.sampled_refs 1091452 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 30526.475636 # Cycle average of tags in use
|
|
system.l2c.total_refs 1952499 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 123882 # number of writebacks
|
|
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
---------- End Simulation Statistics ----------
|