gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json
Andreas Sandberg 877435950c test, arm: Add scripts to test checkpoints
Add a set of scripts to automatically test checkpointing in the
regression framework. The checkpointing tests are similar to the
switcheroo tests, but instead of switching between CPUs, they
checkpoint the system and restore from the checkpoint again. This is
done at regular intervals, typically while booting Linux.

The implementation is fairly straight forward, with the exception that
we have to work around gem5's inability to restore from a checkpoint
after a system has been instantiated. We work around this by forking
off child processes that does the actual simulation and never
instantiate a system in the parent process unless a maximum checkpoint
count is reached (in which case we just simulate the system to
completion in the parent).

Checkpoint testing is currently only enabled 32- and 64-bit ARM
systems using atomic CPUs.

Note: An unfortunate side-effect of forking is that every new process
will overwrite the stats and terminal output from the previous
process. This means that the output directory only contains data from
the last checkpoint.
2015-03-19 04:06:20 -04:00

1620 lines
No EOL
59 KiB
JSON

{
"name": null,
"sim_quantum": 0,
"system": {
"have_virtualization": false,
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"highest_el_is_64": false,
"kernel": "/work/gem5/dist/binaries/vmlinux.aarch64.20140821",
"iobus": {
"slave": {
"peer": [
"system.bridge.master",
"system.realview.clcd.dma",
"system.realview.cf_ctrl.dma",
"system.realview.ide.dma",
"system.realview.ethernet.dma"
],
"role": "SLAVE"
},
"name": "iobus",
"default": {
"peer": "system.realview.pciconfig.pio",
"role": "MASTER"
},
"forward_latency": 1,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"master": {
"peer": [
"system.realview.uart.pio",
"system.realview.realview_io.pio",
"system.realview.timer0.pio",
"system.realview.timer1.pio",
"system.realview.clcd.pio",
"system.realview.hdlcd.pio",
"system.realview.kmi0.pio",
"system.realview.kmi1.pio",
"system.realview.cf_ctrl.pio",
"system.realview.cf_ctrl.config",
"system.realview.rtc.pio",
"system.realview.vram.port",
"system.realview.l2x0_fake.pio",
"system.realview.uart1_fake.pio",
"system.realview.uart2_fake.pio",
"system.realview.uart3_fake.pio",
"system.realview.sp810_fake.pio",
"system.realview.watchdog_fake.pio",
"system.realview.aaci_fake.pio",
"system.realview.lan_fake.pio",
"system.realview.usb_fake.pio",
"system.realview.mmc_fake.pio",
"system.realview.energy_ctrl.pio",
"system.realview.ide.pio",
"system.realview.ide.config",
"system.realview.ethernet.pio",
"system.realview.ethernet.config",
"system.iocache.cpu_side"
],
"role": "MASTER"
},
"response_latency": 2,
"cxx_class": "NoncoherentXBar",
"path": "system.iobus",
"type": "NoncoherentXBar",
"use_default_range": true,
"frontend_latency": 2
},
"symbolfile": "",
"readfile": "/work/gem5/scratch1/gem5/tests/halt.sh",
"have_large_asid_64": false,
"work_end_ckpt_count": 0,
"phys_addr_range_64": 40,
"have_lpae": false,
"cxx_class": "LinuxArmSystem",
"load_offset": 2147483648,
"vncserver": {
"name": "vncserver",
"number": 0,
"frame_capture": false,
"eventq_index": 0,
"capture_exit_frame": -1,
"cxx_class": "VncServer",
"path": "system.vncserver",
"type": "VncServer",
"port": 5900
},
"multi_proc": true,
"early_kernel_symbols": false,
"panic_on_oops": true,
"dtb_filename": "/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb",
"enable_context_switch_stats_dump": false,
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [
"2147483648:2415919103"
],
"realview": {
"hdlcd": {
"dma": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"pixel_clock": 7299,
"vnc": "system.vncserver",
"name": "hdlcd",
"pio": {
"peer": "system.iobus.master[5]",
"role": "SLAVE"
},
"amba_id": 1314816,
"pio_latency": 10000,
"clk_domain": "system.clk_domain",
"system": "system",
"gic": "system.realview.gic",
"int_num": 117,
"eventq_index": 0,
"cxx_class": "HDLcd",
"enable_capture": true,
"path": "system.realview.hdlcd",
"pio_addr": 721420288,
"type": "HDLcd"
},
"mmc_fake": {
"name": "mmc_fake",
"pio": {
"peer": "system.iobus.master[21]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "AmbaFake",
"path": "system.realview.mmc_fake",
"pio_addr": 470089728,
"type": "AmbaFake"
},
"rtc": {
"name": "rtc",
"int_delay": 100000,
"pio": {
"peer": "system.iobus.master[10]",
"role": "SLAVE"
},
"amba_id": 3412017,
"time": "Thu Jan 1 00:00:00 2009",
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"gic": "system.realview.gic",
"int_num": 36,
"eventq_index": 0,
"cxx_class": "PL031",
"path": "system.realview.rtc",
"pio_addr": 471269376,
"type": "PL031"
},
"pci_cfg_gen_offsets": true,
"vgic": {
"system": "system",
"name": "vgic",
"pio": {
"peer": "system.membus.master[3]",
"role": "SLAVE"
},
"clk_domain": "system.clk_domain",
"ppint": 25,
"hv_addr": 738213888,
"gic": "system.realview.gic",
"platform": "system.realview",
"vcpu_addr": 738222080,
"eventq_index": 0,
"cxx_class": "VGic",
"path": "system.realview.vgic",
"type": "VGic",
"pio_delay": 10000
},
"cxx_class": "RealView",
"uart3_fake": {
"name": "uart3_fake",
"pio": {
"peer": "system.iobus.master[15]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "AmbaFake",
"path": "system.realview.uart3_fake",
"pio_addr": 470548480,
"type": "AmbaFake"
},
"realview_io": {
"proc_id1": 335544320,
"name": "realview_io",
"pio": {
"peer": "system.iobus.master[1]",
"role": "SLAVE"
},
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "RealViewCtrl",
"proc_id0": 335544320,
"path": "system.realview.realview_io",
"idreg": 35979264,
"type": "RealViewCtrl",
"pio_addr": 469827584
},
"l2x0_fake": {
"system": "system",
"ret_data8": 255,
"name": "l2x0_fake",
"warn_access": "",
"pio": {
"peer": "system.iobus.master[12]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 4095,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.realview.l2x0_fake",
"pio_addr": 739246080,
"type": "IsaFake",
"ret_data16": 65535
},
"uart1_fake": {
"name": "uart1_fake",
"pio": {
"peer": "system.iobus.master[13]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "AmbaFake",
"path": "system.realview.uart1_fake",
"pio_addr": 470417408,
"type": "AmbaFake"
},
"usb_fake": {
"system": "system",
"ret_data8": 255,
"name": "usb_fake",
"warn_access": "",
"pio": {
"peer": "system.iobus.master[20]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 131071,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.realview.usb_fake",
"pio_addr": 452984832,
"type": "IsaFake",
"ret_data16": 65535
},
"system": "system",
"local_cpu_timer": {
"int_num_watchdog": 30,
"name": "local_cpu_timer",
"pio": {
"peer": "system.membus.master[4]",
"role": "SLAVE"
},
"int_num_timer": 29,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"gic": "system.realview.gic",
"eventq_index": 0,
"cxx_class": "CpuLocalTimer",
"path": "system.realview.local_cpu_timer",
"pio_addr": 738721792,
"type": "CpuLocalTimer"
},
"generic_timer": {
"int_virt": 27,
"name": "generic_timer",
"int_phys": 29,
"cxx_class": "GenericTimer",
"system": "system",
"eventq_index": 0,
"gic": "system.realview.gic",
"path": "system.realview.generic_timer",
"type": "GenericTimer"
},
"gic": {
"it_lines": 128,
"name": "gic",
"dist_addr": 738201600,
"cpu_pio_delay": 10000,
"dist_pio_delay": 10000,
"clk_domain": "system.clk_domain",
"system": "system",
"cpu_addr": 738205696,
"platform": "system.realview",
"int_latency": 10000,
"eventq_index": 0,
"cxx_class": "Pl390",
"pio": {
"peer": "system.membus.master[2]",
"role": "SLAVE"
},
"path": "system.realview.gic",
"type": "Pl390"
},
"timer1": {
"name": "timer1",
"pio": {
"peer": "system.iobus.master[3]",
"role": "SLAVE"
},
"amba_id": 1316868,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"clock0": 1000000,
"clock1": 1000000,
"gic": "system.realview.gic",
"eventq_index": 0,
"cxx_class": "Sp804",
"path": "system.realview.timer1",
"int_num0": 35,
"int_num1": 35,
"type": "Sp804",
"pio_addr": 470941696
},
"timer0": {
"name": "timer0",
"pio": {
"peer": "system.iobus.master[2]",
"role": "SLAVE"
},
"amba_id": 1316868,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"clock0": 1000000,
"clock1": 1000000,
"gic": "system.realview.gic",
"eventq_index": 0,
"cxx_class": "Sp804",
"path": "system.realview.timer0",
"int_num0": 34,
"int_num1": 34,
"type": "Sp804",
"pio_addr": 470876160
},
"uart2_fake": {
"name": "uart2_fake",
"pio": {
"peer": "system.iobus.master[14]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "AmbaFake",
"path": "system.realview.uart2_fake",
"pio_addr": 470482944,
"type": "AmbaFake"
},
"eventq_index": 0,
"energy_ctrl": {
"name": "energy_ctrl",
"pio": {
"peer": "system.iobus.master[22]",
"role": "SLAVE"
},
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "EnergyCtrl",
"path": "system.realview.energy_ctrl",
"dvfs_handler": "system.dvfs_handler",
"type": "EnergyCtrl",
"pio_addr": 470286336
},
"type": "RealView",
"lan_fake": {
"system": "system",
"ret_data8": 255,
"name": "lan_fake",
"warn_access": "",
"pio": {
"peer": "system.iobus.master[19]",
"role": "SLAVE"
},
"ret_bad_addr": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 65535,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.realview.lan_fake",
"pio_addr": 436207616,
"type": "IsaFake",
"ret_data16": 65535
},
"aaci_fake": {
"name": "aaci_fake",
"pio": {
"peer": "system.iobus.master[18]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "AmbaFake",
"path": "system.realview.aaci_fake",
"pio_addr": 470024192,
"type": "AmbaFake"
},
"pciconfig": {
"name": "pciconfig",
"pio": {
"peer": "system.iobus.default",
"role": "SLAVE"
},
"bus": 0,
"pio_latency": 30000,
"clk_domain": "system.clk_domain",
"system": "system",
"platform": "system.realview",
"eventq_index": 0,
"cxx_class": "PciConfigAll",
"path": "system.realview.pciconfig",
"pio_addr": 0,
"type": "PciConfigAll",
"size": 268435456
},
"pci_cfg_base": 805306368,
"path": "system.realview",
"vram": {
"range": "402653184:436207615",
"latency": 30000,
"name": "vram",
"eventq_index": 0,
"clk_domain": "system.clk_domain",
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": false,
"cxx_class": "SimpleMemory",
"path": "system.realview.vram",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.iobus.master[11]",
"role": "SLAVE"
},
"in_addr_map": true
},
"pci_io_base": 788529152,
"nvmem": {
"range": "0:67108863",
"latency": 30000,
"name": "nvmem",
"eventq_index": 0,
"clk_domain": "system.clk_domain",
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"path": "system.realview.nvmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[1]",
"role": "SLAVE"
},
"in_addr_map": true
},
"clcd": {
"dma": {
"peer": "system.iobus.slave[1]",
"role": "MASTER"
},
"pixel_clock": 41667,
"vnc": "system.vncserver",
"name": "clcd",
"pio": {
"peer": "system.iobus.master[4]",
"role": "SLAVE"
},
"amba_id": 1315089,
"pio_latency": 10000,
"clk_domain": "system.clk_domain",
"system": "system",
"gic": "system.realview.gic",
"int_num": 46,
"eventq_index": 0,
"cxx_class": "Pl111",
"enable_capture": true,
"path": "system.realview.clcd",
"pio_addr": 471793664,
"type": "Pl111"
},
"name": "realview",
"uart": {
"terminal": "system.terminal",
"name": "uart",
"int_delay": 100000,
"platform": "system.realview",
"pio": {
"peer": "system.iobus.master[0]",
"role": "SLAVE"
},
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"gic": "system.realview.gic",
"int_num": 37,
"eventq_index": 0,
"end_on_eot": false,
"cxx_class": "Pl011",
"path": "system.realview.uart",
"pio_addr": 470351872,
"type": "Pl011"
},
"watchdog_fake": {
"name": "watchdog_fake",
"pio": {
"peer": "system.iobus.master[17]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "AmbaFake",
"path": "system.realview.watchdog_fake",
"pio_addr": 470745088,
"type": "AmbaFake"
},
"intrctrl": "system.intrctrl",
"kmi1": {
"vnc": "system.vncserver",
"name": "kmi1",
"int_delay": 1000000,
"pio": {
"peer": "system.iobus.master[7]",
"role": "SLAVE"
},
"amba_id": 1314896,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"gic": "system.realview.gic",
"int_num": 45,
"eventq_index": 0,
"is_mouse": true,
"cxx_class": "Pl050",
"path": "system.realview.kmi1",
"pio_addr": 470220800,
"type": "Pl050"
},
"kmi0": {
"vnc": "system.vncserver",
"name": "kmi0",
"int_delay": 1000000,
"pio": {
"peer": "system.iobus.master[6]",
"role": "SLAVE"
},
"amba_id": 1314896,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"gic": "system.realview.gic",
"int_num": 44,
"eventq_index": 0,
"is_mouse": false,
"cxx_class": "Pl050",
"path": "system.realview.kmi0",
"pio_addr": 470155264,
"type": "Pl050"
},
"cf_ctrl": {
"PMCAPNextCapability": 0,
"InterruptPin": 1,
"HeaderType": 0,
"VendorID": 32902,
"MSIXMsgCtrl": 0,
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
"LegacyIOBase": 0,
"pio_latency": 30000,
"platform": "system.realview",
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
"PXCAPDevCapabilities": 0,
"MSIXCAPCapId": 0,
"BAR3Size": 4,
"PXCAPCapabilities": 0,
"SubsystemID": 0,
"PXCAPCapId": 0,
"BAR4": 1,
"BAR1": 471466240,
"BAR0": 471465984,
"BAR3": 1,
"BAR2": 1,
"BAR5": 1,
"PXCAPDevStatus": 0,
"disks": [],
"BAR2Size": 8,
"MSICAPNextCapability": 0,
"ExpansionROM": 0,
"MSICAPMsgCtrl": 0,
"BAR5Size": 0,
"CardbusCIS": 0,
"MSIXPbaOffset": 0,
"MSICAPBaseOffset": 0,
"MaximumLatency": 0,
"BAR2LegacyIO": false,
"LatencyTimer": 0,
"BAR4LegacyIO": false,
"PXCAPLinkStatus": 0,
"PXCAPDevCap2": 0,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"Command": 1,
"SubClassCode": 1,
"pci_func": 0,
"BAR5LegacyIO": false,
"MSICAPMsgData": 0,
"BIST": 0,
"PXCAPDevCtrl2": 0,
"pci_bus": 2,
"InterruptLine": 31,
"MSICAPMsgAddr": 0,
"BAR3LegacyIO": false,
"BAR4Size": 16,
"path": "system.realview.cf_ctrl",
"MinimumGrant": 0,
"Status": 640,
"BAR0Size": 256,
"system": "system",
"name": "cf_ctrl",
"PXCAPNextCapability": 0,
"eventq_index": 0,
"type": "IdeController",
"ctrl_offset": 2,
"PXCAPBaseOffset": 0,
"DeviceID": 28945,
"io_shift": 2,
"CacheLineSize": 0,
"dma": {
"peer": "system.iobus.slave[2]",
"role": "MASTER"
},
"PMCAPCapId": 0,
"config_latency": 20000,
"BAR1Size": 4096,
"pio": {
"peer": "system.iobus.master[8]",
"role": "SLAVE"
},
"pci_dev": 0,
"PMCAPCtrlStatus": 0,
"cxx_class": "IdeController",
"clk_domain": "system.clk_domain",
"SubsystemVendorID": 0,
"PMCAPBaseOffset": 0,
"config": {
"peer": "system.iobus.master[9]",
"role": "SLAVE"
},
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
"MSICAPCapId": 0,
"BAR0LegacyIO": true,
"ProgIF": 133,
"BAR1LegacyIO": true,
"PMCAPCapabilities": 0,
"ClassCode": 1
},
"sp810_fake": {
"name": "sp810_fake",
"pio": {
"peer": "system.iobus.master[16]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": true,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "AmbaFake",
"path": "system.realview.sp810_fake",
"pio_addr": 469893120,
"type": "AmbaFake"
},
"ethernet": {
"PMCAPNextCapability": 0,
"InterruptPin": 1,
"HeaderType": 0,
"VendorID": 32902,
"MSIXMsgCtrl": 0,
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
"hardware_address": "<m5.params.EthernetAddr object at 0x46abfd0>",
"LegacyIOBase": 0,
"pio_latency": 30000,
"platform": "system.realview",
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
"PXCAPDevCapabilities": 0,
"MSIXCAPCapId": 0,
"BAR3Size": 0,
"rx_desc_cache_size": 64,
"PXCAPCapabilities": 0,
"SubsystemID": 4104,
"PXCAPCapId": 0,
"BAR4": 0,
"BAR1": 0,
"BAR0": 0,
"BAR3": 0,
"BAR2": 0,
"BAR5": 0,
"PXCAPDevStatus": 0,
"BAR2Size": 0,
"MSICAPNextCapability": 0,
"ExpansionROM": 0,
"rx_write_delay": 0,
"MSICAPMsgCtrl": 0,
"BAR5Size": 0,
"CardbusCIS": 0,
"MSIXPbaOffset": 0,
"MSICAPBaseOffset": 0,
"MaximumLatency": 0,
"BAR2LegacyIO": false,
"LatencyTimer": 0,
"BAR4LegacyIO": false,
"PXCAPLinkStatus": 0,
"PXCAPDevCap2": 0,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"Command": 0,
"SubClassCode": 0,
"pci_func": 0,
"BAR5LegacyIO": false,
"MSICAPMsgData": 0,
"BIST": 0,
"PXCAPDevCtrl2": 0,
"pci_bus": 0,
"InterruptLine": 1,
"fetch_delay": 10000,
"MSICAPMsgAddr": 0,
"BAR3LegacyIO": false,
"BAR4Size": 0,
"path": "system.realview.ethernet",
"MinimumGrant": 255,
"phy_epid": 896,
"Status": 0,
"BAR0Size": 131072,
"system": "system",
"name": "ethernet",
"PXCAPNextCapability": 0,
"eventq_index": 0,
"type": "IGbE",
"tx_fifo_size": 393216,
"PXCAPBaseOffset": 0,
"DeviceID": 4213,
"tx_read_delay": 0,
"CacheLineSize": 0,
"dma": {
"peer": "system.iobus.slave[4]",
"role": "MASTER"
},
"PMCAPCapId": 0,
"tx_desc_cache_size": 64,
"config_latency": 20000,
"BAR1Size": 0,
"pio": {
"peer": "system.iobus.master[25]",
"role": "SLAVE"
},
"pci_dev": 0,
"PMCAPCtrlStatus": 0,
"cxx_class": "IGbE",
"wb_delay": 10000,
"fetch_comp_delay": 10000,
"clk_domain": "system.clk_domain",
"SubsystemVendorID": 32902,
"PMCAPBaseOffset": 0,
"config": {
"peer": "system.iobus.master[26]",
"role": "SLAVE"
},
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
"MSICAPCapId": 0,
"BAR0LegacyIO": false,
"ProgIF": 0,
"BAR1LegacyIO": false,
"wb_comp_delay": 10000,
"PMCAPCapabilities": 0,
"ClassCode": 2,
"rx_fifo_size": 393216,
"phy_pid": 680
},
"ide": {
"PMCAPNextCapability": 0,
"InterruptPin": 2,
"HeaderType": 0,
"VendorID": 32902,
"MSIXMsgCtrl": 0,
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
"LegacyIOBase": 0,
"pio_latency": 30000,
"platform": "system.realview",
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
"PXCAPDevCapabilities": 0,
"MSIXCAPCapId": 0,
"BAR3Size": 4,
"PXCAPCapabilities": 0,
"SubsystemID": 0,
"PXCAPCapId": 0,
"BAR4": 1,
"BAR1": 1,
"BAR0": 1,
"BAR3": 1,
"BAR2": 1,
"BAR5": 1,
"PXCAPDevStatus": 0,
"disks": [
"system.cf0"
],
"BAR2Size": 8,
"MSICAPNextCapability": 0,
"ExpansionROM": 0,
"MSICAPMsgCtrl": 0,
"BAR5Size": 0,
"CardbusCIS": 0,
"MSIXPbaOffset": 0,
"MSICAPBaseOffset": 0,
"MaximumLatency": 0,
"BAR2LegacyIO": false,
"LatencyTimer": 0,
"BAR4LegacyIO": false,
"PXCAPLinkStatus": 0,
"PXCAPDevCap2": 0,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"Command": 0,
"SubClassCode": 1,
"pci_func": 0,
"BAR5LegacyIO": false,
"MSICAPMsgData": 0,
"BIST": 0,
"PXCAPDevCtrl2": 0,
"pci_bus": 0,
"InterruptLine": 2,
"MSICAPMsgAddr": 0,
"BAR3LegacyIO": false,
"BAR4Size": 16,
"path": "system.realview.ide",
"MinimumGrant": 0,
"Status": 640,
"BAR0Size": 8,
"system": "system",
"name": "ide",
"PXCAPNextCapability": 0,
"eventq_index": 0,
"type": "IdeController",
"ctrl_offset": 0,
"PXCAPBaseOffset": 0,
"DeviceID": 28945,
"io_shift": 0,
"CacheLineSize": 0,
"dma": {
"peer": "system.iobus.slave[3]",
"role": "MASTER"
},
"PMCAPCapId": 0,
"config_latency": 20000,
"BAR1Size": 4,
"pio": {
"peer": "system.iobus.master[23]",
"role": "SLAVE"
},
"pci_dev": 1,
"PMCAPCtrlStatus": 0,
"cxx_class": "IdeController",
"clk_domain": "system.clk_domain",
"SubsystemVendorID": 0,
"PMCAPBaseOffset": 0,
"config": {
"peer": "system.iobus.master[24]",
"role": "SLAVE"
},
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
"MSICAPCapId": 0,
"BAR0LegacyIO": false,
"ProgIF": 133,
"BAR1LegacyIO": false,
"PMCAPCapabilities": 0,
"ClassCode": 1
}
},
"membus": {
"default": {
"peer": "system.membus.badaddr_responder.pio",
"role": "MASTER"
},
"slave": {
"peer": [
"system.realview.hdlcd.dma",
"system.system_port",
"system.cpu.l2cache.mem_side",
"system.iocache.mem_side"
],
"role": "SLAVE"
},
"name": "membus",
"badaddr_responder": {
"system": "system",
"ret_data8": 255,
"name": "badaddr_responder",
"warn_access": "warn",
"pio": {
"peer": "system.membus.default",
"role": "SLAVE"
},
"ret_bad_addr": true,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
"eventq_index": 0,
"update_data": false,
"ret_data64": 18446744073709551615,
"cxx_class": "IsaFake",
"path": "system.membus.badaddr_responder",
"pio_addr": 0,
"type": "IsaFake",
"ret_data16": 65535
},
"snoop_filter": null,
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"system": "system",
"width": 16,
"eventq_index": 0,
"master": {
"peer": [
"system.bridge.slave",
"system.realview.nvmem.port",
"system.realview.gic.pio",
"system.realview.vgic.pio",
"system.realview.local_cpu_timer.pio",
"system.physmem.port"
],
"role": "MASTER"
},
"response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus",
"snoop_response_latency": 4,
"type": "CoherentXBar",
"use_default_range": false,
"frontend_latency": 3
},
"panic_on_panic": true,
"eventq_index": 0,
"iocache": {
"is_top_level": true,
"prefetcher": null,
"clk_domain": "system.clk_domain",
"write_buffers": 8,
"response_latency": 50,
"cxx_class": "BaseCache",
"size": 1024,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 50,
"clk_domain": "system.clk_domain",
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
"path": "system.iocache.tags",
"block_size": 64,
"type": "LRU",
"size": 1024
},
"system": "system",
"max_miss_count": 0,
"eventq_index": 0,
"mem_side": {
"peer": "system.membus.slave[3]",
"role": "MASTER"
},
"mshrs": 20,
"forward_snoops": false,
"hit_latency": 50,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"2147483648:2415919103"
],
"assoc": 8,
"prefetch_on_access": false,
"path": "system.iocache",
"name": "iocache",
"type": "BaseCache",
"sequential_access": false,
"cpu_side": {
"peer": "system.iobus.master[27]",
"role": "SLAVE"
},
"two_queue": false
},
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "LinuxArmSystem",
"bridge": {
"ranges": [
"788529152:805306367",
"721420288:725614591",
"805306368:1073741823",
"1073741824:1610612735",
"402653184:469762047",
"469762048:536870911"
],
"slave": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"name": "bridge",
"req_size": 16,
"clk_domain": "system.clk_domain",
"delay": 50000,
"eventq_index": 0,
"master": {
"peer": "system.iobus.slave[0]",
"role": "MASTER"
},
"cxx_class": "Bridge",
"path": "system.bridge",
"resp_size": 16,
"type": "Bridge"
},
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1",
"physmem": [
{
"range": "2147483648:2415919103",
"latency": 30000,
"name": "physmem",
"eventq_index": 0,
"clk_domain": "system.clk_domain",
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[5]",
"role": "SLAVE"
},
"in_addr_map": true
}
],
"terminal": {
"name": "terminal",
"output": true,
"number": 0,
"intr_control": "system.intrctrl",
"eventq_index": 0,
"cxx_class": "Terminal",
"path": "system.terminal",
"type": "Terminal",
"port": 3456
},
"reset_addr_64": 0,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"is_stage2": false,
"eventq_index": 0,
"cxx_class": "ArmISA::TLB",
"walker": {
"name": "walker",
"is_stage2": false,
"clk_domain": "system.cpu_clk_domain",
"sys": "system",
"eventq_index": 0,
"cxx_class": "ArmISA::TableWalker",
"path": "system.cpu.itb.walker",
"type": "ArmTableWalker",
"port": {
"peer": "system.cpu.toL2Bus.slave[2]",
"role": "MASTER"
},
"num_squash_per_cycle": 2
},
"path": "system.cpu.itb",
"type": "ArmTLB",
"size": 64
},
"simulate_data_stalls": false,
"istage2_mmu": {
"name": "istage2_mmu",
"tlb": "system.cpu.itb",
"sys": "system",
"stage2_tlb": {
"name": "stage2_tlb",
"is_stage2": true,
"eventq_index": 0,
"cxx_class": "ArmISA::TLB",
"walker": {
"name": "walker",
"is_stage2": true,
"clk_domain": "system.cpu_clk_domain",
"sys": "system",
"eventq_index": 0,
"cxx_class": "ArmISA::TableWalker",
"path": "system.cpu.istage2_mmu.stage2_tlb.walker",
"type": "ArmTableWalker",
"num_squash_per_cycle": 2
},
"path": "system.cpu.istage2_mmu.stage2_tlb",
"type": "ArmTLB",
"size": 32
},
"eventq_index": 0,
"cxx_class": "ArmISA::Stage2MMU",
"path": "system.cpu.istage2_mmu",
"type": "ArmStage2MMU"
},
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "AtomicSimpleCPU",
"max_loads_all_threads": 0,
"system": "system",
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"width": 1,
"checker": null,
"eventq_index": 0,
"toL2Bus": {
"slave": {
"peer": [
"system.cpu.icache.mem_side",
"system.cpu.dcache.mem_side",
"system.cpu.itb.walker.port",
"system.cpu.dtb.walker.port"
],
"role": "SLAVE"
},
"name": "toL2Bus",
"snoop_filter": null,
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"system": "system",
"width": 32,
"eventq_index": 0,
"master": {
"peer": [
"system.cpu.l2cache.cpu_side"
],
"role": "MASTER"
},
"response_latency": 1,
"cxx_class": "CoherentXBar",
"path": "system.cpu.toL2Bus",
"snoop_response_latency": 1,
"type": "CoherentXBar",
"use_default_range": false,
"frontend_latency": 1
},
"do_quiesce": true,
"type": "AtomicSimpleCPU",
"fastmem": false,
"profile": 0,
"icache_port": {
"peer": "system.cpu.icache.cpu_side",
"role": "MASTER"
},
"icache": {
"is_top_level": true,
"prefetcher": null,
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "BaseCache",
"size": 32768,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 2,
"clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 1,
"cxx_class": "LRU",
"path": "system.cpu.icache.tags",
"block_size": 64,
"type": "LRU",
"size": 32768
},
"system": "system",
"max_miss_count": 0,
"eventq_index": 0,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[0]",
"role": "MASTER"
},
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
],
"assoc": 1,
"prefetch_on_access": false,
"path": "system.cpu.icache",
"name": "icache",
"type": "BaseCache",
"sequential_access": false,
"cpu_side": {
"peer": "system.cpu.icache_port",
"role": "SLAVE"
},
"two_queue": false
},
"interrupts": {
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "ArmInterrupts",
"name": "interrupts",
"cxx_class": "ArmISA::Interrupts"
},
"dcache_port": {
"peer": "system.cpu.dcache.cpu_side",
"role": "MASTER"
},
"socket_id": 0,
"max_insts_all_threads": 0,
"dstage2_mmu": {
"name": "dstage2_mmu",
"tlb": "system.cpu.dtb",
"sys": "system",
"stage2_tlb": {
"name": "stage2_tlb",
"is_stage2": true,
"eventq_index": 0,
"cxx_class": "ArmISA::TLB",
"walker": {
"name": "walker",
"is_stage2": true,
"clk_domain": "system.cpu_clk_domain",
"sys": "system",
"eventq_index": 0,
"cxx_class": "ArmISA::TableWalker",
"path": "system.cpu.dstage2_mmu.stage2_tlb.walker",
"type": "ArmTableWalker",
"num_squash_per_cycle": 2
},
"path": "system.cpu.dstage2_mmu.stage2_tlb",
"type": "ArmTLB",
"size": 32
},
"eventq_index": 0,
"cxx_class": "ArmISA::Stage2MMU",
"path": "system.cpu.dstage2_mmu",
"type": "ArmStage2MMU"
},
"l2cache": {
"is_top_level": false,
"prefetcher": null,
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
"response_latency": 20,
"cxx_class": "BaseCache",
"size": 4194304,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 20,
"clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
"path": "system.cpu.l2cache.tags",
"block_size": 64,
"type": "LRU",
"size": 4194304
},
"system": "system",
"max_miss_count": 0,
"eventq_index": 0,
"mem_side": {
"peer": "system.membus.slave[2]",
"role": "MASTER"
},
"mshrs": 20,
"forward_snoops": true,
"hit_latency": 20,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"0:18446744073709551615"
],
"assoc": 8,
"prefetch_on_access": false,
"path": "system.cpu.l2cache",
"name": "l2cache",
"type": "BaseCache",
"sequential_access": false,
"cpu_side": {
"peer": "system.cpu.toL2Bus.master[0]",
"role": "SLAVE"
},
"two_queue": false
},
"path": "system.cpu",
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [],
"name": "cpu",
"dtb": {
"name": "dtb",
"is_stage2": false,
"eventq_index": 0,
"cxx_class": "ArmISA::TLB",
"walker": {
"name": "walker",
"is_stage2": false,
"clk_domain": "system.cpu_clk_domain",
"sys": "system",
"eventq_index": 0,
"cxx_class": "ArmISA::TableWalker",
"path": "system.cpu.dtb.walker",
"type": "ArmTableWalker",
"port": {
"peer": "system.cpu.toL2Bus.slave[3]",
"role": "MASTER"
},
"num_squash_per_cycle": 2
},
"path": "system.cpu.dtb",
"type": "ArmTLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"simulate_inst_stalls": false,
"progress_interval": 0,
"branchPred": null,
"dcache": {
"is_top_level": true,
"prefetcher": null,
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "BaseCache",
"size": 32768,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 2,
"clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 4,
"cxx_class": "LRU",
"path": "system.cpu.dcache.tags",
"block_size": 64,
"type": "LRU",
"size": 32768
},
"system": "system",
"max_miss_count": 0,
"eventq_index": 0,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[1]",
"role": "MASTER"
},
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
],
"assoc": 4,
"prefetch_on_access": false,
"path": "system.cpu.dcache",
"name": "dcache",
"type": "BaseCache",
"sequential_access": false,
"cpu_side": {
"peer": "system.cpu.dcache_port",
"role": "SLAVE"
},
"two_queue": false
},
"isa": [
{
"pmu": null,
"id_pfr1": 4113,
"id_pfr0": 49,
"id_isar1": 34677009,
"id_isar0": 34607377,
"id_isar3": 17899825,
"id_isar2": 555950401,
"id_isar5": 0,
"id_isar4": 268501314,
"cxx_class": "ArmISA::ISA",
"id_aa64mmfr1_el1": 0,
"id_aa64pfr1_el1": 0,
"system": "system",
"eventq_index": 0,
"type": "ArmISA",
"id_aa64dfr1_el1": 0,
"fpsid": 1090793632,
"id_mmfr0": 270536963,
"id_mmfr1": 0,
"id_mmfr2": 19070976,
"id_mmfr3": 34611729,
"id_aa64mmfr0_el1": 15728642,
"id_aa64dfr0_el1": 1052678,
"path": "system.cpu.isa",
"id_aa64isar0_el1": 0,
"name": "isa",
"midr": 1091551472,
"id_aa64afr0_el1": 0,
"id_aa64isar1_el1": 0,
"id_aa64afr1_el1": 0,
"id_aa64pfr0_el1": 17
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"gic_cpu_addr": 738205696,
"work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0,
"machine_type": "VExpress_EMM64",
"flags_addr": 469827632,
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"cf0": {
"driveID": "master",
"name": "cf0",
"image": {
"read_only": false,
"name": "image",
"cxx_class": "CowDiskImage",
"eventq_index": 0,
"child": {
"read_only": true,
"name": "child",
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.cf0.image.child",
"image_file": "/work/gem5/dist/disks/linaro-minimal-aarch64.img",
"type": "RawDiskImage"
},
"path": "system.cf0.image",
"image_file": "",
"type": "CowDiskImage",
"table_size": 65536
},
"delay": 1000000,
"eventq_index": 0,
"cxx_class": "IdeDisk",
"path": "system.cf0",
"type": "IdeDisk"
},
"boot_release_addr": 65528,
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
"system_port": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"load_addr_mask": 268435455,
"work_item_id": -1,
"intrctrl": {
"name": "intrctrl",
"sys": "system",
"eventq_index": 0,
"cxx_class": "IntrControl",
"path": "system.intrctrl",
"type": "IntrControl"
},
"have_security": false,
"atags_addr": 134217728,
"memories": [
"system.physmem",
"system.realview.nvmem",
"system.realview.vram"
],
"work_begin_cpu_id_exit": -1,
"boot_loader": "/work/gem5/dist/binaries/boot_emm.arm64",
"num_work_ids": 16
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": true
}