1483496803
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5) inadvertently fixed a bug in the Minor CPU model which caused it to treat software prefetches as regular loads. Prior to this changeset, Minor did an ad-hoc generation of memory commands that left out the PF check; because it now uses the common code that the other CPU models use, it generates prefetches properly. These stat changes reflect the fact that the Minor model now issues SoftPFReqs.
16 lines
996 B
Text
Executable file
16 lines
996 B
Text
Executable file
gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Mar 15 2015 20:30:55
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gem5 started Mar 15 2015 20:31:14
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gem5 executing on zizzer2
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
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Selected 64-bit ARM architecture, updating default disk image...
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch64.20140821
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0: system.cpu.isa: ISA system set to: 0x404afc0 0x404afc0
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info: Using bootloader at address 0x10
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info: Using kernel entry physical address at 0x80080000
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info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 51609998980000 because m5_exit instruction encountered
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