gem5/cpu/base_cpu.cc
Nathan Binkert 9023f5c96d - Clean up and factor out all of the binning code into a
single place so it's easier to work with.
-  Add support for binning kernel/user/idle time separately from
lisa's binning stuff, but make the two compatible.
-  KernelStats used to directly implement the pImpl idiom, but
it makes more sense to just remove the level of indirection and
make the exec context have a pointer to the stats.
-  Factor common code out of LinuxSystem and Tru64System and put
it into the System base class.  While doing that, make all
constructors take a pointer to a parameter struct instead of
naming the parameters individually to make it much easier to add
parameters to these classes.

SConscript:
    Move the function tracking and binning stuff around.
arch/alpha/ev5.cc:
    kernelStats is now a pointer
arch/alpha/pseudo_inst.cc:
    kernelStats is now a pointer
    the parameters to the system have been moved into their own
    struct
base/trace.hh:
    provide a little functor class for wrapping a string that
    can allow you to define name() in any scope very simply
    for use with DPRINTF
cpu/base_cpu.cc:
    New order of arguments for consistency.
cpu/exec_context.cc:
    kernelStats no longer has the level of indirection in it,
    execContext has the indirection now.  so, kernelStats is a pointer.
    We also need a pointer to the kernelBinning stuff from the system
    and we need to figure out if we want to do binning or not.
    Move a whole bunch of code into kern_binning.cc so it's all
    in the same place.
cpu/exec_context.hh:
    We want pointers to the kernel binning/stats stuff and we'll
    have the exec_context and system have the level of indirection
    instead of having the extra layer in the kernel stats class.
cpu/simple_cpu/simple_cpu.cc:
    call through the exec context to do the special binning
    stuff.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
    Re-organize the stats stuff and remove the level of indirection
    (that was there to simplify building) and move the binning stuff
    into its own class/file.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/system.cc:
sim/system.hh:
    move lots of common system code into the base system class so
    that it can be shared between linux, tru64, and whatever else
    we decide to support in the future.

    Make the constructor take a pointer to a parameter struct so that
    it is easier to pass parameters to the parent.
kern/system_events.cc:
    move the majority of the binning code into the Kernel::Binning class
    in the kern_binning file
kern/system_events.hh:
    FnEvents only need to know the bin
    create the Idle start event to find the PCBB of the idle
    process when it starts.
kern/tru64/tru64_events.cc:
    memCtrl -> memctrl
sim/process.cc:
sim/process.hh:
    re-order args for consistency

--HG--
extra : convert_revision : 86cb39738c41fcd680f2aad125c9dde000227b2b
2004-08-20 11:35:31 -04:00

262 lines
8 KiB
C++

/*
* Copyright (c) 2002-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <string>
#include <sstream>
#include <iostream>
#include "cpu/base_cpu.hh"
#include "base/cprintf.hh"
#include "cpu/exec_context.hh"
#include "base/misc.hh"
#include "sim/param.hh"
#include "sim/sim_events.hh"
using namespace std;
vector<BaseCPU *> BaseCPU::cpuList;
// This variable reflects the max number of threads in any CPU. Be
// careful to only use it once all the CPUs that you care about have
// been initialized
int maxThreadsPerCPU = 1;
#ifdef FULL_SYSTEM
BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
Counter max_insts_any_thread,
Counter max_insts_all_threads,
Counter max_loads_any_thread,
Counter max_loads_all_threads,
System *_system, Tick freq)
: SimObject(_name), frequency(freq),
number_of_threads(_number_of_threads), system(_system)
#else
BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
Counter max_insts_any_thread,
Counter max_insts_all_threads,
Counter max_loads_any_thread,
Counter max_loads_all_threads)
: SimObject(_name), number_of_threads(_number_of_threads)
#endif
{
// add self to global list of CPUs
cpuList.push_back(this);
if (number_of_threads > maxThreadsPerCPU)
maxThreadsPerCPU = number_of_threads;
// allocate per-thread instruction-based event queues
comInstEventQueue = new (EventQueue *)[number_of_threads];
for (int i = 0; i < number_of_threads; ++i)
comInstEventQueue[i] = new EventQueue("instruction-based event queue");
//
// set up instruction-count-based termination events, if any
//
if (max_insts_any_thread != 0)
for (int i = 0; i < number_of_threads; ++i)
new SimExitEvent(comInstEventQueue[i], max_insts_any_thread,
"a thread reached the max instruction count");
if (max_insts_all_threads != 0) {
// allocate & initialize shared downcounter: each event will
// decrement this when triggered; simulation will terminate
// when counter reaches 0
int *counter = new int;
*counter = number_of_threads;
for (int i = 0; i < number_of_threads; ++i)
new CountedExitEvent(comInstEventQueue[i],
"all threads reached the max instruction count",
max_insts_all_threads, *counter);
}
// allocate per-thread load-based event queues
comLoadEventQueue = new (EventQueue *)[number_of_threads];
for (int i = 0; i < number_of_threads; ++i)
comLoadEventQueue[i] = new EventQueue("load-based event queue");
//
// set up instruction-count-based termination events, if any
//
if (max_loads_any_thread != 0)
for (int i = 0; i < number_of_threads; ++i)
new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread,
"a thread reached the max load count");
if (max_loads_all_threads != 0) {
// allocate & initialize shared downcounter: each event will
// decrement this when triggered; simulation will terminate
// when counter reaches 0
int *counter = new int;
*counter = number_of_threads;
for (int i = 0; i < number_of_threads; ++i)
new CountedExitEvent(comLoadEventQueue[i],
"all threads reached the max load count",
max_loads_all_threads, *counter);
}
#ifdef FULL_SYSTEM
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
#endif
}
void
BaseCPU::regStats()
{
using namespace Stats;
numCycles
.name(name() + ".numCycles")
.desc("number of cpu cycles simulated")
;
int size = execContexts.size();
if (size > 1) {
for (int i = 0; i < size; ++i) {
stringstream namestr;
ccprintf(namestr, "%s.ctx%d", name(), i);
execContexts[i]->regStats(namestr.str());
}
} else if (size == 1)
execContexts[0]->regStats(name());
}
void
BaseCPU::registerExecContexts()
{
for (int i = 0; i < execContexts.size(); ++i) {
ExecContext *xc = execContexts[i];
int cpu_id;
#ifdef FULL_SYSTEM
cpu_id = system->registerExecContext(xc);
#else
cpu_id = xc->process->registerExecContext(xc);
#endif
xc->cpu_id = cpu_id;
}
}
void
BaseCPU::switchOut()
{
// default: do nothing
}
void
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
assert(execContexts.size() == oldCPU->execContexts.size());
for (int i = 0; i < execContexts.size(); ++i) {
ExecContext *newXC = execContexts[i];
ExecContext *oldXC = oldCPU->execContexts[i];
newXC->takeOverFrom(oldXC);
assert(newXC->cpu_id == oldXC->cpu_id);
#ifdef FULL_SYSTEM
system->replaceExecContext(newXC, newXC->cpu_id);
#else
assert(newXC->process == oldXC->process);
newXC->process->replaceExecContext(newXC, newXC->cpu_id);
#endif
}
#ifdef FULL_SYSTEM
for (int i = 0; i < NumInterruptLevels; ++i)
interrupts[i] = oldCPU->interrupts[i];
intstatus = oldCPU->intstatus;
#endif
}
#ifdef FULL_SYSTEM
void
BaseCPU::post_interrupt(int int_num, int index)
{
DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
if (int_num < 0 || int_num >= NumInterruptLevels)
panic("int_num out of bounds\n");
if (index < 0 || index >= sizeof(uint64_t) * 8)
panic("int_num out of bounds\n");
AlphaISA::check_interrupts = 1;
interrupts[int_num] |= 1 << index;
intstatus |= (ULL(1) << int_num);
}
void
BaseCPU::clear_interrupt(int int_num, int index)
{
DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
if (int_num < 0 || int_num >= NumInterruptLevels)
panic("int_num out of bounds\n");
if (index < 0 || index >= sizeof(uint64_t) * 8)
panic("int_num out of bounds\n");
interrupts[int_num] &= ~(1 << index);
if (interrupts[int_num] == 0)
intstatus &= ~(ULL(1) << int_num);
}
void
BaseCPU::clear_interrupts()
{
DPRINTF(Interrupt, "Interrupts all cleared\n");
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
}
void
BaseCPU::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
SERIALIZE_SCALAR(intstatus);
}
void
BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
UNSERIALIZE_SCALAR(intstatus);
}
#endif // FULL_SYSTEM
DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)