126 lines
3.7 KiB
C++
126 lines
3.7 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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/**
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* @file
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* Declaration of a non-full system Page Table.
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*/
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#ifndef __PAGE_TABLE__
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#define __PAGE_TABLE__
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#include <string>
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#include "sim/faults.hh"
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#include "arch/isa_traits.hh"
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#include "arch/tlb.hh"
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#include "base/hashmap.hh"
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#include "mem/request.hh"
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#include "sim/host.hh"
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#include "sim/serialize.hh"
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class Process;
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/**
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* Page Table Declaration.
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*/
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class PageTable
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{
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protected:
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typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
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typedef PTable::iterator PTableItr;
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PTable pTable;
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struct cacheElement {
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Addr vaddr;
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TheISA::TlbEntry entry;
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};
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struct cacheElement pTableCache[3];
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const Addr pageSize;
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const Addr offsetMask;
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Process *process;
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public:
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PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
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~PageTable();
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Addr pageAlign(Addr a) { return (a & ~offsetMask); }
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Addr pageOffset(Addr a) { return (a & offsetMask); }
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void allocate(Addr vaddr, int64_t size);
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/**
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* Lookup function
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* @param vaddr The virtual address.
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* @return entry The page table entry corresponding to vaddr.
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*/
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bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
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/**
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* Translate function
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* @param vaddr The virtual address.
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* @return Physical address from translation.
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*/
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bool translate(Addr vaddr, Addr &paddr);
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/**
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* Perform a translation on the memory request, fills in paddr
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* field of req.
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* @param req The memory request.
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*/
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Fault translate(RequestPtr req);
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/**
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* Update the page table cache.
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* @param vaddr virtual address (page aligned) to check
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* @param pte page table entry to return
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*/
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inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
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{
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pTableCache[2].entry = pTableCache[1].entry;
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pTableCache[2].vaddr = pTableCache[1].vaddr;
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pTableCache[1].entry = pTableCache[0].entry;
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pTableCache[1].vaddr = pTableCache[0].vaddr;
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pTableCache[0].entry = entry;
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pTableCache[0].vaddr = vaddr;
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif
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