197 lines
5.7 KiB
C++
197 lines
5.7 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Kevin Lim
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*/
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#ifndef __ARCH_ALPHA_INTERRUPT_HH__
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#define __ARCH_ALPHA_INTERRUPT_HH__
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#include "arch/alpha/faults.hh"
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#include "arch/alpha/isa_traits.hh"
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#include "base/compiler.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "params/AlphaInterrupts.hh"
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#include "sim/sim_object.hh"
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namespace AlphaISA {
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class Interrupts : public SimObject
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{
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private:
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bool newInfoSet;
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int newIpl;
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int newSummary;
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BaseCPU * cpu;
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protected:
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uint64_t interrupts[NumInterruptLevels];
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uint64_t intstatus;
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public:
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typedef AlphaInterruptsParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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Interrupts(Params * p) : SimObject(p), cpu(NULL)
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{
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memset(interrupts, 0, sizeof(interrupts));
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intstatus = 0;
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newInfoSet = false;
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}
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void
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setCPU(BaseCPU * _cpu)
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{
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cpu = _cpu;
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}
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void
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post(int int_num, int index)
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{
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DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
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if (int_num < 0 || int_num >= NumInterruptLevels)
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panic("int_num out of bounds\n");
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if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
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panic("int_num out of bounds\n");
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interrupts[int_num] |= 1 << index;
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intstatus |= (ULL(1) << int_num);
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}
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void
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clear(int int_num, int index)
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{
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DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
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if (int_num < 0 || int_num >= NumInterruptLevels)
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panic("int_num out of bounds\n");
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if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
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panic("int_num out of bounds\n");
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interrupts[int_num] &= ~(1 << index);
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if (interrupts[int_num] == 0)
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intstatus &= ~(ULL(1) << int_num);
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}
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void
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clearAll()
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{
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DPRINTF(Interrupt, "Interrupts all cleared\n");
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memset(interrupts, 0, sizeof(interrupts));
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intstatus = 0;
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}
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void
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serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
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SERIALIZE_SCALAR(intstatus);
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}
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void
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unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
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UNSERIALIZE_SCALAR(intstatus);
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}
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bool
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checkInterrupts(ThreadContext *tc) const
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{
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return (intstatus != 0) && !(tc->readPC() & 0x3);
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}
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Fault
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getInterrupt(ThreadContext *tc)
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{
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uint64_t ipl = 0;
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uint64_t summary = 0;
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if (tc->readMiscRegNoEffect(IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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if (tc->readMiscRegNoEffect(IPR_SIRR)) {
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for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
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// See table 4-19 of 21164 hardware reference
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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}
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uint64_t interrupts = intstatus;
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if (interrupts) {
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for (uint64_t i = INTLEVEL_EXTERNAL_MIN;
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i < INTLEVEL_EXTERNAL_MAX; i++) {
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if (interrupts & (ULL(1) << i)) {
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// See table 4-19 of 21164 hardware reference
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ipl = i;
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summary |= (ULL(1) << i);
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}
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}
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}
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if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
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newIpl = ipl;
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newSummary = summary;
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newInfoSet = true;
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
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return new InterruptFault;
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} else {
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return NoFault;
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}
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}
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void
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updateIntrInfo(ThreadContext *tc)
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{
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assert(newInfoSet);
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tc->setMiscRegNoEffect(IPR_ISR, newSummary);
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tc->setMiscRegNoEffect(IPR_INTID, newIpl);
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newInfoSet = false;
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}
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};
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_INTERRUPT_HH__
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