e196d20d9d
arch/alpha/arguments.cc:
rather than returning 0, put a panic in... it will actually make us fix
this rather than scratching our respective heads
base/loader/object_file.cc:
base/loader/object_file.hh:
Object loader now takes a port rather than a translating port
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
sim/process.cc:
Make translating port a type of port rather than anything special
cpu/simple/cpu.cc:
no need to grab a port from the cpu anymore
mem/physical.cc:
add an additional type of port to physicalmemory called "functional"
Only used for functional accesses (loading binaries/syscall emu)
mem/port.hh:
make readBlok/writeBlob virtual so translating port can do the
translation first
mem/translating_port.cc:
mem/translating_port.hh:
Make TranslatingPort inherit from Port
sim/system.cc:
header file that doesn't exit removed
--HG--
extra : convert_revision : 89b08f6146bba61f5605678d736055feab2fe6f7
70 lines
2.8 KiB
C++
70 lines
2.8 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_TRANSLATING_PROT_HH__
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#define __MEM_TRANSLATING_PROT_HH__
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#include "mem/port.hh"
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class PageTable;
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class TranslatingPort : public Port
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{
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private:
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PageTable *pTable;
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bool allocating;
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TranslatingPort(const TranslatingPort &specmem);
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const TranslatingPort &operator=(const TranslatingPort &specmem);
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public:
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TranslatingPort(PageTable *p_table, bool alloc = false);
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virtual ~TranslatingPort();
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public:
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bool tryReadBlob(Addr addr, uint8_t *p, int size);
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bool tryWriteBlob(Addr addr, uint8_t *p, int size);
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bool tryMemsetBlob(Addr addr, uint8_t val, int size);
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bool tryWriteString(Addr addr, const char *str);
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bool tryReadString(std::string &str, Addr addr);
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virtual void readBlob(Addr addr, uint8_t *p, int size);
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virtual void writeBlob(Addr addr, uint8_t *p, int size);
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virtual void memsetBlob(Addr addr, uint8_t val, int size);
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void writeString(Addr addr, const char *str);
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void readString(std::string &str, Addr addr);
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virtual bool recvTiming(Packet &pkt) { panic("TransPort is UniDir"); }
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virtual Tick recvAtomic(Packet &pkt) { panic("TransPort is UniDir"); }
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virtual void recvFunctional(Packet &pkt) { panic("TransPort is UniDir"); }
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virtual void recvStatusChange(Status status) {panic("TransPort is UniDir");}
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};
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#endif
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