b38f67d5b7
requestTime -> time
responseTime -> packet.time
Make CPU and memory able to connect to the bus
dev/io_device.cc:
update for request and packet both having a time
hand platform off to port for eventual selection of request modes
dev/io_device.hh:
update for request and packet both havig a time
hand platform off to port for eventual selection of request modes
mem/bus.hh:
Add a device map struct that maps a range to a portId
- Which needs work it theory it should be an interval tree
- but it is a list and works fine right now
Add a function called findPort which returns port for an addr range
Add a deviceBlockSize function that really shouldn't exist, but it
was easier than fixing the translating port
mem/packet.hh:
add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
remove requestTime/responseTime for just time in request which
is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
Fix for new bus object
--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
107 lines
3.5 KiB
C++
107 lines
3.5 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file Decleration of a request, the overall memory request consisting of
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the parts of the request that are persistent throughout the transaction.
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*/
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#ifndef __MEM_REQUEST_HH__
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#define __MEM_REQUEST_HH__
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#include "arch/isa_traits.hh"
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class Request;
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class CpuRequest;
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typedef Request* RequestPtr;
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typedef CpuRequest* CpuRequestPtr;
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/** The request is a Load locked/store conditional. */
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const unsigned LOCKED = 0x001;
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/** The virtual address is also the physical address. */
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const unsigned PHYSICAL = 0x002;
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/** The request is an ALPHA VPTE pal access (hw_ld). */
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const unsigned VPTE = 0x004;
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/** Use the alternate mode bits in ALPHA. */
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const unsigned ALTMODE = 0x008;
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/** The request is to an uncacheable address. */
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const unsigned UNCACHEABLE = 0x010;
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/** The request should not cause a page fault. */
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const unsigned NO_FAULT = 0x020;
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/** The request should be prefetched into the exclusive state. */
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const unsigned PF_EXCLUSIVE = 0x100;
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/** The request should be marked as LRU. */
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const unsigned EVICT_NEXT = 0x200;
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class Request
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{
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//@todo Make Accesor functions, make these private.
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public:
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/** The physical address of the request. */
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Addr paddr;
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/** whether this req came from the CPU or not **DO we need this??***/
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bool nicReq;
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/** The size of the request. */
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int size;
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/** The time this request was started. Used to calculate latencies. */
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Tick time;
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/** Destination address if this is a block copy. */
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Addr copyDest;
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uint32_t flags;
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};
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class CpuRequest : public Request
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{
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//@todo Make Accesor functions, make these private.
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public:
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/** The virtual address of the request. */
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Addr vaddr;
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/** The address space ID. */
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int asid;
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/** The return value of store conditional. */
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uint64_t scResult;
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/** The cpu number for statistics. */
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int cpuNum;
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/** The requesting thread id. */
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int threadNum;
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/** program counter of initiating access; for tracing/debugging */
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Addr pc;
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};
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#endif // __MEM_REQUEST_HH__
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