7a0d5aafe4
This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work.
214 lines
8.6 KiB
Python
214 lines
8.6 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from Ruby import create_topology
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#
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# Note: the L1 Cache latency is only used by the sequencer on fast path hits
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#
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class L1Cache(RubyCache):
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latency = 3
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#
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# Note: the L2 Cache latency is not currently used
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#
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class L2Cache(RubyCache):
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latency = 15
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def define_options(parser):
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return
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def create_system(options, system, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
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panic("This script requires the MOESI_CMP_directory protocol to be built.")
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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l2_cntrl_nodes = []
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dir_cntrl_nodes = []
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dma_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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l2_bits = int(math.log(options.num_l2caches, 2))
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block_size_bits = int(math.log(options.cacheline_size, 2))
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for i in xrange(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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#
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l1i_cache = L1Cache(size = options.l1i_size,
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assoc = options.l1i_assoc,
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start_index_bit = block_size_bits,
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is_icache = True)
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l1d_cache = L1Cache(size = options.l1d_size,
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assoc = options.l1d_assoc,
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start_index_bit = block_size_bits,
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is_icache = False)
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l1_cntrl = L1Cache_Controller(version = i,
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L1Icache = l1i_cache,
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L1Dcache = l1d_cache,
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l2_select_num_bits = l2_bits,
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send_evictions = (
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options.cpu_type == "detailed"),
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transitions_per_cycle = options.ports,
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clk_domain=system.cpu[i].clk_domain,
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(version = i,
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icache = l1i_cache,
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dcache = l1d_cache,
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clk_domain=system.cpu[i].clk_domain,
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ruby_system = ruby_system)
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l1_cntrl.sequencer = cpu_seq
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exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
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# Add controllers and sequencers to the appropriate lists
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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# Connect the L1 controllers and the network
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l1_cntrl.requestFromL1Cache = ruby_system.network.slave
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l1_cntrl.responseFromL1Cache = ruby_system.network.slave
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l1_cntrl.requestToL1Cache = ruby_system.network.master
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l1_cntrl.responseToL1Cache = ruby_system.network.master
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l2_index_start = block_size_bits + l2_bits
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for i in xrange(options.num_l2caches):
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#
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# First create the Ruby objects associated with this cpu
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#
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l2_cache = L2Cache(size = options.l2_size,
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assoc = options.l2_assoc,
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start_index_bit = l2_index_start)
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l2_cntrl = L2Cache_Controller(version = i,
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L2cache = l2_cache,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
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l2_cntrl_nodes.append(l2_cntrl)
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# Connect the L2 controllers and the network
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l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
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l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
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l2_cntrl.responseFromL2Cache = ruby_system.network.slave
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l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
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l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
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l2_cntrl.responseToL2Cache = ruby_system.network.master
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phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
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assert(phys_mem_size % options.num_dirs == 0)
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mem_module_size = phys_mem_size / options.num_dirs
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# Run each of the ruby memory controllers at a ratio of the frequency of
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# the ruby system.
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# clk_divider value is a fix to pass regression.
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ruby_system.memctrl_clk_domain = DerivedClockDomain(
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clk_domain=ruby_system.clk_domain,
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clk_divider=3)
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for i in xrange(options.num_dirs):
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#
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# Create the Ruby objects associated with the directory controller
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#
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mem_cntrl = RubyMemoryControl(
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clk_domain = ruby_system.memctrl_clk_domain,
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version = i,
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ruby_system = ruby_system)
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dir_size = MemorySize('0B')
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dir_size.value = mem_module_size
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dir_cntrl = Directory_Controller(version = i,
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directory = \
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RubyDirectoryMemory(version = i,
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size = dir_size,
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use_map = options.use_map),
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memBuffer = mem_cntrl,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
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dir_cntrl_nodes.append(dir_cntrl)
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# Connect the directory controllers and the network
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dir_cntrl.requestToDir = ruby_system.network.master
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dir_cntrl.responseToDir = ruby_system.network.master
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dir_cntrl.responseFromDir = ruby_system.network.slave
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dir_cntrl.forwardFromDir = ruby_system.network.slave
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i,
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ruby_system = ruby_system)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l1_cntrl_nodes + \
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l2_cntrl_nodes + \
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dir_cntrl_nodes + \
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dma_cntrl_nodes
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topology = create_topology(all_cntrls, options)
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return (cpu_sequencers, dir_cntrl_nodes, topology)
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