e65de3f5ca
This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge. The change is needed to allow interleaved memory controllers in the system.
175 lines
6.3 KiB
Python
175 lines
6.3 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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from abc import ABCMeta, abstractmethod
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import m5
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from m5.objects import *
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from m5.proxy import *
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m5.util.addToPath('../configs/common')
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import FSConfig
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from Caches import *
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class BaseSystem(object):
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"""Base system builder.
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This class provides some basic functionality for creating an ARM
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system with the usual peripherals (caches, GIC, etc.). It allows
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customization by defining separate methods for different parts of
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the initialization process.
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"""
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__metaclass__ = ABCMeta
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def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
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num_cpus=1, checker=False):
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"""Initialize a simple ARM system.
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Keyword Arguments:
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mem_mode -- String describing the memory mode (timing or atomic)
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cpu_class -- CPU class to use
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num_cpus -- Number of CPUs to instantiate
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checker -- Set to True to add checker CPUs
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"""
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self.mem_mode = mem_mode
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self.cpu_class = cpu_class
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self.num_cpus = num_cpus
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self.checker = checker
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def create_cpus(self):
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"""Return a list of CPU objects to add to a system."""
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cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
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for i in range(self.num_cpus) ]
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if self.checker:
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for c in cpus:
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c.addCheckerCpu()
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return cpus
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def create_caches_private(self, cpu):
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"""Add private caches to a CPU.
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Arguments:
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cpu -- CPU instance to work on.
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"""
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cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
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L1Cache(size='32kB', assoc=4))
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def create_caches_shared(self, system):
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"""Add shared caches to a system.
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Arguments:
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system -- System to work on.
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Returns:
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A bus that CPUs should use to connect to the shared cache.
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"""
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system.toL2Bus = CoherentBus(clock='2GHz')
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system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
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system.l2c.cpu_side = system.toL2Bus.master
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system.l2c.mem_side = system.membus.slave
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return system.toL2Bus
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def init_cpu(self, system, cpu):
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"""Initialize a CPU.
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Arguments:
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system -- System to work on.
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cpu -- CPU to initialize.
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"""
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cpu.createInterruptController()
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def init_system(self, system):
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"""Initialize a system.
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Arguments:
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system -- System to initialize.
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"""
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system.cpu = self.create_cpus()
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sha_bus = self.create_caches_shared(system)
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for cpu in system.cpu:
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self.create_caches_private(cpu)
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self.init_cpu(system, cpu)
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cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
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system.membus)
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@abstractmethod
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def create_system(self):
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"""Create an return an initialized system."""
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pass
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@abstractmethod
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def create_root(self):
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"""Create and return a simulation root using the system
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defined by this class."""
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pass
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class BaseFSSystem(BaseSystem):
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"""Basic full system builder."""
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def __init__(self, **kwargs):
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BaseSystem.__init__(self, **kwargs)
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def init_system(self, system):
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BaseSystem.init_system(self, system)
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#create the iocache
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system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges)
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system.iocache.cpu_side = system.iobus.master
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system.iocache.mem_side = system.membus.slave
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def create_root(self):
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system = self.create_system()
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m5.ticks.setGlobalFrequency('1THz')
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return Root(full_system=True, system=system)
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class BaseFSSystemUniprocessor(BaseFSSystem):
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"""Basic full system builder for uniprocessor systems.
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Note: This class is only really needed to provide backwards
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compatibility in existing test cases.
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"""
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def __init__(self, **kwargs):
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BaseFSSystem.__init__(self, **kwargs)
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def create_caches_private(self, cpu):
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cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
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L1Cache(size='32kB', assoc=4),
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L2Cache(size='4MB', assoc=8))
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def create_caches_shared(self, system):
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return None
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