e097c4fb18
Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
775 lines
31 KiB
C++
775 lines
31 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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svcCode = '''
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#if FULL_SYSTEM
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fault = new SupervisorCall;
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#else
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fault = new SupervisorCall(machInst);
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#endif
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'''
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svcIop = InstObjParams("svc", "Svc", "PredOp",
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{ "code": svcCode,
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"predicate_test": predicateTest }, ["IsSyscall"])
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header_output = BasicDeclare.subst(svcIop)
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decoder_output = BasicConstructor.subst(svcIop)
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exec_output = PredOpExecute.subst(svcIop)
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}};
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let {{
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header_output = decoder_output = exec_output = ""
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mrsCpsrCode = '''
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Dest = (Cpsr | CondCodesF | CondCodesGE) & 0xF8FF03DF
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'''
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mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
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{ "code": mrsCpsrCode,
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"predicate_test": condPredicateTest },
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["IsSerializeBefore"])
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header_output += MrsDeclare.subst(mrsCpsrIop)
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decoder_output += MrsConstructor.subst(mrsCpsrIop)
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exec_output += PredOpExecute.subst(mrsCpsrIop)
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mrsSpsrCode = "Dest = Spsr"
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mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
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{ "code": mrsSpsrCode,
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"predicate_test": predicateTest },
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["IsSerializeBefore"])
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header_output += MrsDeclare.subst(mrsSpsrIop)
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decoder_output += MrsConstructor.subst(mrsSpsrIop)
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exec_output += PredOpExecute.subst(mrsSpsrIop)
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msrCpsrRegCode = '''
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SCTLR sctlr = Sctlr;
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, Op1,
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byteMask, false, sctlr.nmfi);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodesF = CondCodesMaskF & newCpsr;
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CondCodesGE = CondCodesMaskGE & newCpsr;
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'''
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msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
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{ "code": msrCpsrRegCode,
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"predicate_test": condPredicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += MsrRegDeclare.subst(msrCpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
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exec_output += PredOpExecute.subst(msrCpsrRegIop)
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msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
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msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
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{ "code": msrSpsrRegCode,
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"predicate_test": predicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += MsrRegDeclare.subst(msrSpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
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exec_output += PredOpExecute.subst(msrSpsrRegIop)
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msrCpsrImmCode = '''
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SCTLR sctlr = Sctlr;
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, imm,
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byteMask, false, sctlr.nmfi);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodesF = CondCodesMaskF & newCpsr;
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CondCodesGE = CondCodesMaskGE & newCpsr;
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'''
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msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
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{ "code": msrCpsrImmCode,
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"predicate_test": condPredicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += MsrImmDeclare.subst(msrCpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
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exec_output += PredOpExecute.subst(msrCpsrImmIop)
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msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
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msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
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{ "code": msrSpsrImmCode,
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"predicate_test": predicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += MsrImmDeclare.subst(msrSpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
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exec_output += PredOpExecute.subst(msrSpsrImmIop)
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revCode = '''
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uint32_t val = Op1;
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Dest = swap_byte(val);
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'''
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revIop = InstObjParams("rev", "Rev", "RegRegOp",
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{ "code": revCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(revIop)
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decoder_output += RegRegOpConstructor.subst(revIop)
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exec_output += PredOpExecute.subst(revIop)
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rev16Code = '''
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uint32_t val = Op1;
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Dest = (bits(val, 15, 8) << 0) |
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(bits(val, 7, 0) << 8) |
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(bits(val, 31, 24) << 16) |
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(bits(val, 23, 16) << 24);
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'''
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rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
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{ "code": rev16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(rev16Iop)
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decoder_output += RegRegOpConstructor.subst(rev16Iop)
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exec_output += PredOpExecute.subst(rev16Iop)
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revshCode = '''
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uint16_t val = Op1;
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Dest = sext<16>(swap_byte(val));
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'''
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revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
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{ "code": revshCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(revshIop)
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decoder_output += RegRegOpConstructor.subst(revshIop)
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exec_output += PredOpExecute.subst(revshIop)
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rbitCode = '''
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uint8_t *opBytes = (uint8_t *)&Op1;
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uint32_t resTemp;
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uint8_t *destBytes = (uint8_t *)&resTemp;
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// This reverses the bytes and bits of the input, or so says the
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// internet.
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for (int i = 0; i < 4; i++) {
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uint32_t temp = opBytes[i];
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temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
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destBytes[3 - i] = (temp * 0x10101) >> 16;
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}
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Dest = resTemp;
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'''
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rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
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{ "code": rbitCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(rbitIop)
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decoder_output += RegRegOpConstructor.subst(rbitIop)
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exec_output += PredOpExecute.subst(rbitIop)
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clzCode = '''
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Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
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'''
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clzIop = InstObjParams("clz", "Clz", "RegRegOp",
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{ "code": clzCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(clzIop)
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decoder_output += RegRegOpConstructor.subst(clzIop)
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exec_output += PredOpExecute.subst(clzIop)
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ssatCode = '''
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int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
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int32_t res;
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if (satInt(res, operand, imm))
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CpsrQ = 1 << 27;
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Dest = res;
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'''
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ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
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{ "code": ssatCode,
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"predicate_test": condPredicateTest }, [])
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header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
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decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
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exec_output += PredOpExecute.subst(ssatIop)
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usatCode = '''
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int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
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int32_t res;
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if (uSatInt(res, operand, imm))
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CpsrQ = 1 << 27;
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Dest = res;
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'''
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usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
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{ "code": usatCode,
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"predicate_test": condPredicateTest }, [])
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header_output += RegImmRegShiftOpDeclare.subst(usatIop)
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decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
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exec_output += PredOpExecute.subst(usatIop)
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ssat16Code = '''
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int32_t res;
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uint32_t resTemp = 0;
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int32_t argLow = sext<16>(bits(Op1, 15, 0));
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int32_t argHigh = sext<16>(bits(Op1, 31, 16));
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if (satInt(res, argLow, imm))
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CpsrQ = 1 << 27;
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replaceBits(resTemp, 15, 0, res);
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if (satInt(res, argHigh, imm))
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CpsrQ = 1 << 27;
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replaceBits(resTemp, 31, 16, res);
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Dest = resTemp;
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'''
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ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
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{ "code": ssat16Code,
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"predicate_test": condPredicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(ssat16Iop)
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decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
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exec_output += PredOpExecute.subst(ssat16Iop)
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usat16Code = '''
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int32_t res;
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uint32_t resTemp = 0;
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int32_t argLow = sext<16>(bits(Op1, 15, 0));
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int32_t argHigh = sext<16>(bits(Op1, 31, 16));
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if (uSatInt(res, argLow, imm))
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CpsrQ = 1 << 27;
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replaceBits(resTemp, 15, 0, res);
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if (uSatInt(res, argHigh, imm))
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CpsrQ = 1 << 27;
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replaceBits(resTemp, 31, 16, res);
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Dest = resTemp;
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'''
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usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
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{ "code": usat16Code,
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"predicate_test": condPredicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(usat16Iop)
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decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
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exec_output += PredOpExecute.subst(usat16Iop)
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sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
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{ "code":
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"Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(sxtbIop)
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decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
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exec_output += PredOpExecute.subst(sxtbIop)
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sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
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{ "code":
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'''
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Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
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Op1;
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''',
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
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decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
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exec_output += PredOpExecute.subst(sxtabIop)
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sxtb16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
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replaceBits(resTemp, 31, 16,
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sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
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Dest = resTemp;
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'''
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sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
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{ "code": sxtb16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
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decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
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exec_output += PredOpExecute.subst(sxtb16Iop)
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sxtab16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
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bits(Op1, 15, 0));
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replaceBits(resTemp, 31, 16,
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sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
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bits(Op1, 31, 16));
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Dest = resTemp;
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'''
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sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
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{ "code": sxtab16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
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decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
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exec_output += PredOpExecute.subst(sxtab16Iop)
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sxthCode = '''
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uint64_t rotated = (uint32_t)Op1;
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rotated = (rotated | (rotated << 32)) >> imm;
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Dest = sext<16>((uint16_t)rotated);
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'''
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sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
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{ "code": sxthCode,
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(sxthIop)
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decoder_output += RegImmRegOpConstructor.subst(sxthIop)
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exec_output += PredOpExecute.subst(sxthIop)
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sxtahCode = '''
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uint64_t rotated = (uint32_t)Op2;
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rotated = (rotated | (rotated << 32)) >> imm;
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Dest = sext<16>((uint16_t)rotated) + Op1;
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'''
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sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
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{ "code": sxtahCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
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decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
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exec_output += PredOpExecute.subst(sxtahIop)
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uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
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{ "code": "Dest = (uint8_t)(Op1.ud >> imm);",
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(uxtbIop)
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decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
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exec_output += PredOpExecute.subst(uxtbIop)
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uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
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{ "code":
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"Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
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decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
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exec_output += PredOpExecute.subst(uxtabIop)
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uxtb16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
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replaceBits(resTemp, 31, 16,
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(uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
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Dest = resTemp;
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'''
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uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
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{ "code": uxtb16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
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decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
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exec_output += PredOpExecute.subst(uxtb16Iop)
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uxtab16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
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bits(Op1, 15, 0));
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replaceBits(resTemp, 31, 16,
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(uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
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bits(Op1, 31, 16));
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Dest = resTemp;
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'''
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uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
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{ "code": uxtab16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
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decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
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exec_output += PredOpExecute.subst(uxtab16Iop)
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uxthCode = '''
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uint64_t rotated = (uint32_t)Op1;
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rotated = (rotated | (rotated << 32)) >> imm;
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Dest = (uint16_t)rotated;
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'''
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uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
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{ "code": uxthCode,
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(uxthIop)
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decoder_output += RegImmRegOpConstructor.subst(uxthIop)
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exec_output += PredOpExecute.subst(uxthIop)
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uxtahCode = '''
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uint64_t rotated = (uint32_t)Op2;
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rotated = (rotated | (rotated << 32)) >> imm;
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Dest = (uint16_t)rotated + Op1;
|
|
'''
|
|
uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
|
|
{ "code": uxtahCode,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
|
|
decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
|
|
exec_output += PredOpExecute.subst(uxtahIop)
|
|
|
|
selCode = '''
|
|
uint32_t resTemp = 0;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int low = i * 8;
|
|
int high = low + 7;
|
|
replaceBits(resTemp, high, low,
|
|
bits(CondCodesGE, 16 + i) ?
|
|
bits(Op1, high, low) : bits(Op2, high, low));
|
|
}
|
|
Dest = resTemp;
|
|
'''
|
|
selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
|
|
{ "code": selCode,
|
|
"predicate_test": condPredicateTest }, [])
|
|
header_output += RegRegRegOpDeclare.subst(selIop)
|
|
decoder_output += RegRegRegOpConstructor.subst(selIop)
|
|
exec_output += PredOpExecute.subst(selIop)
|
|
|
|
usad8Code = '''
|
|
uint32_t resTemp = 0;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int low = i * 8;
|
|
int high = low + 7;
|
|
int32_t diff = bits(Op1, high, low) -
|
|
bits(Op2, high, low);
|
|
resTemp += ((diff < 0) ? -diff : diff);
|
|
}
|
|
Dest = resTemp;
|
|
'''
|
|
usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
|
|
{ "code": usad8Code,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += RegRegRegOpDeclare.subst(usad8Iop)
|
|
decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
|
|
exec_output += PredOpExecute.subst(usad8Iop)
|
|
|
|
usada8Code = '''
|
|
uint32_t resTemp = 0;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int low = i * 8;
|
|
int high = low + 7;
|
|
int32_t diff = bits(Op1, high, low) -
|
|
bits(Op2, high, low);
|
|
resTemp += ((diff < 0) ? -diff : diff);
|
|
}
|
|
Dest = Op3 + resTemp;
|
|
'''
|
|
usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
|
|
{ "code": usada8Code,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
|
|
decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
|
|
exec_output += PredOpExecute.subst(usada8Iop)
|
|
|
|
bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
|
|
bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
|
|
header_output += BasicDeclare.subst(bkptIop)
|
|
decoder_output += BasicConstructor.subst(bkptIop)
|
|
exec_output += BasicExecute.subst(bkptIop)
|
|
|
|
nopIop = InstObjParams("nop", "NopInst", "PredOp", \
|
|
{ "code" : "", "predicate_test" : predicateTest },
|
|
['IsNop'])
|
|
header_output += BasicDeclare.subst(nopIop)
|
|
decoder_output += BasicConstructor.subst(nopIop)
|
|
exec_output += PredOpExecute.subst(nopIop)
|
|
|
|
yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
|
|
{ "code" : "", "predicate_test" : predicateTest })
|
|
header_output += BasicDeclare.subst(yieldIop)
|
|
decoder_output += BasicConstructor.subst(yieldIop)
|
|
exec_output += PredOpExecute.subst(yieldIop)
|
|
|
|
wfeCode = '''
|
|
#if FULL_SYSTEM
|
|
if (SevMailbox == 1) {
|
|
SevMailbox = 0;
|
|
PseudoInst::quiesceSkip(xc->tcBase());
|
|
} else {
|
|
PseudoInst::quiesce(xc->tcBase());
|
|
}
|
|
#endif
|
|
'''
|
|
wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
|
|
{ "code" : wfeCode, "predicate_test" : predicateTest },
|
|
["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
|
|
header_output += BasicDeclare.subst(wfeIop)
|
|
decoder_output += BasicConstructor.subst(wfeIop)
|
|
exec_output += QuiescePredOpExecute.subst(wfeIop)
|
|
|
|
wfiCode = '''
|
|
#if FULL_SYSTEM
|
|
// WFI doesn't sleep if interrupts are pending (masked or not)
|
|
if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
|
|
PseudoInst::quiesceSkip(xc->tcBase());
|
|
} else {
|
|
PseudoInst::quiesce(xc->tcBase());
|
|
}
|
|
#endif
|
|
'''
|
|
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
|
|
{ "code" : wfiCode, "predicate_test" : predicateTest },
|
|
["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
|
|
header_output += BasicDeclare.subst(wfiIop)
|
|
decoder_output += BasicConstructor.subst(wfiIop)
|
|
exec_output += QuiescePredOpExecute.subst(wfiIop)
|
|
|
|
sevCode = '''
|
|
// Need a way for O3 to not scoreboard these accesses as pipe flushes.
|
|
SevMailbox = 1;
|
|
System *sys = xc->tcBase()->getSystemPtr();
|
|
for (int x = 0; x < sys->numContexts(); x++) {
|
|
ThreadContext *oc = sys->getThreadContext(x);
|
|
if (oc == xc->tcBase())
|
|
continue;
|
|
// Only wake if they were sleeping
|
|
if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
|
|
oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
|
|
PseudoInst::wakeCPU(xc->tcBase(), x);
|
|
}
|
|
}
|
|
'''
|
|
sevIop = InstObjParams("sev", "SevInst", "PredOp", \
|
|
{ "code" : sevCode, "predicate_test" : predicateTest },
|
|
["IsNonSpeculative", "IsSquashAfter"])
|
|
header_output += BasicDeclare.subst(sevIop)
|
|
decoder_output += BasicConstructor.subst(sevIop)
|
|
exec_output += PredOpExecute.subst(sevIop)
|
|
|
|
itIop = InstObjParams("it", "ItInst", "PredOp", \
|
|
{ "code" : ";",
|
|
"predicate_test" : predicateTest },
|
|
["IsNonSpeculative", "IsSerializeAfter"])
|
|
header_output += BasicDeclare.subst(itIop)
|
|
decoder_output += BasicConstructor.subst(itIop)
|
|
exec_output += PredOpExecute.subst(itIop)
|
|
unknownCode = '''
|
|
#if FULL_SYSTEM
|
|
return new UndefinedInstruction;
|
|
#else
|
|
return new UndefinedInstruction(machInst, true);
|
|
#endif
|
|
'''
|
|
unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
|
|
{ "code": unknownCode,
|
|
"predicate_test": predicateTest })
|
|
header_output += BasicDeclare.subst(unknownIop)
|
|
decoder_output += BasicConstructor.subst(unknownIop)
|
|
exec_output += PredOpExecute.subst(unknownIop)
|
|
|
|
ubfxCode = '''
|
|
Dest = bits(Op1, imm2, imm1);
|
|
'''
|
|
ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
|
|
{ "code": ubfxCode,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
|
|
decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
|
|
exec_output += PredOpExecute.subst(ubfxIop)
|
|
|
|
sbfxCode = '''
|
|
int32_t resTemp = bits(Op1, imm2, imm1);
|
|
Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
|
|
'''
|
|
sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
|
|
{ "code": sbfxCode,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
|
|
decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
|
|
exec_output += PredOpExecute.subst(sbfxIop)
|
|
|
|
bfcCode = '''
|
|
Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
|
|
'''
|
|
bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
|
|
{ "code": bfcCode,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += RegRegImmImmOpDeclare.subst(bfcIop)
|
|
decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
|
|
exec_output += PredOpExecute.subst(bfcIop)
|
|
|
|
bfiCode = '''
|
|
uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
|
|
Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
|
|
'''
|
|
bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
|
|
{ "code": bfiCode,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += RegRegImmImmOpDeclare.subst(bfiIop)
|
|
decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
|
|
exec_output += PredOpExecute.subst(bfiIop)
|
|
|
|
mrc15code = '''
|
|
CPSR cpsr = Cpsr;
|
|
if (cpsr.mode == MODE_USER)
|
|
#if FULL_SYSTEM
|
|
return new UndefinedInstruction;
|
|
#else
|
|
return new UndefinedInstruction(false, mnemonic);
|
|
#endif
|
|
Dest = MiscOp1;
|
|
'''
|
|
|
|
mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
|
|
{ "code": mrc15code,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += RegRegOpDeclare.subst(mrc15Iop)
|
|
decoder_output += RegRegOpConstructor.subst(mrc15Iop)
|
|
exec_output += PredOpExecute.subst(mrc15Iop)
|
|
|
|
|
|
mcr15code = '''
|
|
CPSR cpsr = Cpsr;
|
|
if (cpsr.mode == MODE_USER)
|
|
#if FULL_SYSTEM
|
|
return new UndefinedInstruction;
|
|
#else
|
|
return new UndefinedInstruction(false, mnemonic);
|
|
#endif
|
|
MiscDest = Op1;
|
|
'''
|
|
mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
|
|
{ "code": mcr15code,
|
|
"predicate_test": predicateTest },
|
|
["IsSerializeAfter","IsNonSpeculative"])
|
|
header_output += RegRegOpDeclare.subst(mcr15Iop)
|
|
decoder_output += RegRegOpConstructor.subst(mcr15Iop)
|
|
exec_output += PredOpExecute.subst(mcr15Iop)
|
|
|
|
mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
|
|
{ "code": "Dest = MiscOp1;",
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += RegRegOpDeclare.subst(mrc15UserIop)
|
|
decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
|
|
exec_output += PredOpExecute.subst(mrc15UserIop)
|
|
|
|
mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
|
|
{ "code": "MiscDest = Op1",
|
|
"predicate_test": predicateTest },
|
|
["IsSerializeAfter","IsNonSpeculative"])
|
|
header_output += RegRegOpDeclare.subst(mcr15UserIop)
|
|
decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
|
|
exec_output += PredOpExecute.subst(mcr15UserIop)
|
|
|
|
enterxCode = '''
|
|
NextThumb = true;
|
|
NextJazelle = true;
|
|
'''
|
|
enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
|
|
{ "code": enterxCode,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += BasicDeclare.subst(enterxIop)
|
|
decoder_output += BasicConstructor.subst(enterxIop)
|
|
exec_output += PredOpExecute.subst(enterxIop)
|
|
|
|
leavexCode = '''
|
|
NextThumb = true;
|
|
NextJazelle = false;
|
|
'''
|
|
leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
|
|
{ "code": leavexCode,
|
|
"predicate_test": predicateTest }, [])
|
|
header_output += BasicDeclare.subst(leavexIop)
|
|
decoder_output += BasicConstructor.subst(leavexIop)
|
|
exec_output += PredOpExecute.subst(leavexIop)
|
|
|
|
setendCode = '''
|
|
CPSR cpsr = Cpsr;
|
|
cpsr.e = imm;
|
|
Cpsr = cpsr;
|
|
'''
|
|
setendIop = InstObjParams("setend", "Setend", "ImmOp",
|
|
{ "code": setendCode,
|
|
"predicate_test": predicateTest },
|
|
["IsSerializeAfter","IsNonSpeculative"])
|
|
header_output += ImmOpDeclare.subst(setendIop)
|
|
decoder_output += ImmOpConstructor.subst(setendIop)
|
|
exec_output += PredOpExecute.subst(setendIop)
|
|
|
|
clrexCode = '''
|
|
LLSCLock = 0;
|
|
'''
|
|
clrexIop = InstObjParams("clrex", "Clrex","PredOp",
|
|
{ "code": clrexCode,
|
|
"predicate_test": predicateTest },[])
|
|
header_output += BasicDeclare.subst(clrexIop)
|
|
decoder_output += BasicConstructor.subst(clrexIop)
|
|
exec_output += PredOpExecute.subst(clrexIop)
|
|
|
|
isbCode = '''
|
|
fault = new FlushPipe;
|
|
'''
|
|
isbIop = InstObjParams("isb", "Isb", "PredOp",
|
|
{"code": isbCode,
|
|
"predicate_test": predicateTest},
|
|
['IsSerializeAfter'])
|
|
header_output += BasicDeclare.subst(isbIop)
|
|
decoder_output += BasicConstructor.subst(isbIop)
|
|
exec_output += PredOpExecute.subst(isbIop)
|
|
|
|
dsbCode = '''
|
|
fault = new FlushPipe;
|
|
'''
|
|
dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
|
|
{"code": dsbCode,
|
|
"predicate_test": predicateTest},
|
|
['IsMemBarrier', 'IsSerializeAfter'])
|
|
header_output += BasicDeclare.subst(dsbIop)
|
|
decoder_output += BasicConstructor.subst(dsbIop)
|
|
exec_output += PredOpExecute.subst(dsbIop)
|
|
|
|
dmbCode = '''
|
|
'''
|
|
dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
|
|
{"code": dmbCode,
|
|
"predicate_test": predicateTest},
|
|
['IsMemBarrier'])
|
|
header_output += BasicDeclare.subst(dmbIop)
|
|
decoder_output += BasicConstructor.subst(dmbIop)
|
|
exec_output += PredOpExecute.subst(dmbIop)
|
|
|
|
dbgCode = '''
|
|
'''
|
|
dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
|
|
{"code": dbgCode,
|
|
"predicate_test": predicateTest})
|
|
header_output += BasicDeclare.subst(dbgIop)
|
|
decoder_output += BasicConstructor.subst(dbgIop)
|
|
exec_output += PredOpExecute.subst(dbgIop)
|
|
|
|
cpsCode = '''
|
|
uint32_t mode = bits(imm, 4, 0);
|
|
uint32_t f = bits(imm, 5);
|
|
uint32_t i = bits(imm, 6);
|
|
uint32_t a = bits(imm, 7);
|
|
bool setMode = bits(imm, 8);
|
|
bool enable = bits(imm, 9);
|
|
CPSR cpsr = Cpsr;
|
|
SCTLR sctlr = Sctlr;
|
|
if (cpsr.mode != MODE_USER) {
|
|
if (enable) {
|
|
if (f) cpsr.f = 0;
|
|
if (i) cpsr.i = 0;
|
|
if (a) cpsr.a = 0;
|
|
} else {
|
|
if (f && !sctlr.nmfi) cpsr.f = 1;
|
|
if (i) cpsr.i = 1;
|
|
if (a) cpsr.a = 1;
|
|
}
|
|
if (setMode) {
|
|
cpsr.mode = mode;
|
|
}
|
|
}
|
|
Cpsr = cpsr;
|
|
'''
|
|
cpsIop = InstObjParams("cps", "Cps", "ImmOp",
|
|
{ "code": cpsCode,
|
|
"predicate_test": predicateTest },
|
|
["IsSerializeAfter","IsNonSpeculative"])
|
|
header_output += ImmOpDeclare.subst(cpsIop)
|
|
decoder_output += ImmOpConstructor.subst(cpsIop)
|
|
exec_output += PredOpExecute.subst(cpsIop)
|
|
}};
|