952 lines
110 KiB
Text
952 lines
110 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.060132 # Number of seconds simulated
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sim_ticks 60131512500 # Number of ticks simulated
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final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 320494 # Simulator instruction rate (inst/s)
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host_op_rate 409865 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 271758284 # Simulator tick rate (ticks/s)
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host_mem_usage 281048 # Number of bytes of host memory used
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host_seconds 221.27 # Real time elapsed on the host
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sim_insts 70915150 # Number of instructions simulated
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sim_ops 90690106 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory
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system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory
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system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 128515 # Number of read requests accepted
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system.physmem.writeReqs 86552 # Number of write requests accepted
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system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
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system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 8086 # Per bank write bursts
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system.physmem.perBankRdBursts::1 8335 # Per bank write bursts
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system.physmem.perBankRdBursts::2 8257 # Per bank write bursts
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system.physmem.perBankRdBursts::3 8155 # Per bank write bursts
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system.physmem.perBankRdBursts::4 8301 # Per bank write bursts
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system.physmem.perBankRdBursts::5 8413 # Per bank write bursts
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system.physmem.perBankRdBursts::6 8070 # Per bank write bursts
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system.physmem.perBankRdBursts::7 7917 # Per bank write bursts
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system.physmem.perBankRdBursts::8 8054 # Per bank write bursts
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system.physmem.perBankRdBursts::9 7613 # Per bank write bursts
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system.physmem.perBankRdBursts::10 7771 # Per bank write bursts
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system.physmem.perBankRdBursts::11 7825 # Per bank write bursts
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system.physmem.perBankRdBursts::12 7888 # Per bank write bursts
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system.physmem.perBankRdBursts::13 7870 # Per bank write bursts
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system.physmem.perBankRdBursts::14 7981 # Per bank write bursts
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system.physmem.perBankRdBursts::15 7974 # Per bank write bursts
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system.physmem.perBankWrBursts::0 5400 # Per bank write bursts
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system.physmem.perBankWrBursts::1 5549 # Per bank write bursts
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system.physmem.perBankWrBursts::2 5475 # Per bank write bursts
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system.physmem.perBankWrBursts::3 5349 # Per bank write bursts
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system.physmem.perBankWrBursts::4 5387 # Per bank write bursts
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system.physmem.perBankWrBursts::5 5586 # Per bank write bursts
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system.physmem.perBankWrBursts::6 5325 # Per bank write bursts
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system.physmem.perBankWrBursts::7 5260 # Per bank write bursts
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system.physmem.perBankWrBursts::8 5187 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5135 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5306 # Per bank write bursts
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system.physmem.perBankWrBursts::11 5279 # Per bank write bursts
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system.physmem.perBankWrBursts::12 5541 # Per bank write bursts
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system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
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system.physmem.perBankWrBursts::14 5706 # Per bank write bursts
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system.physmem.perBankWrBursts::15 5441 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 60131481000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 128515 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 86552 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads
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system.physmem.totQLat 3049168000 # Total ticks spent queuing
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system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 1.79 # Data bus utilization in percentage
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system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing
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system.physmem.readRowHits 112228 # Number of row buffer hits during reads
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system.physmem.writeRowHits 69923 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes
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system.physmem.avgGap 279594.18 # Average gap between requests
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system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ)
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system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ)
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system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ)
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system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ)
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system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ)
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system.physmem_0.averagePower 386.918165 # Core power per rank (mW)
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system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank
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system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states
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system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states
|
|
system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ)
|
|
system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ)
|
|
system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 383.198268 # Core power per rank (mW)
|
|
system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank
|
|
system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.branchPred.lookups 14827796 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
|
system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups.
|
|
system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits.
|
|
system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses.
|
|
system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
|
system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 120263025 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 70915150 # Number of instructions committed
|
|
system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.695872 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.589667 # IPC: instructions per cycle
|
|
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction
|
|
system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction
|
|
system.cpu.op_class_0::MemWrite 20555707 22.67% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::total 90690106 # Class of committed instruction
|
|
system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements 156451 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 42605460 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 299788 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 128145 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187431 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187431 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125 # average overall mshr miss latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements 43545 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1851.999823 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1851.999823 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.904297 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.904297 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 898 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 25048343 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 25048343 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 25048343 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 45588 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042263500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 1042263500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1042263500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 1042263500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1042263500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 1042263500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 25093931 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 25093931 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 25093931 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 22862.672194 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 22862.672194 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.writebacks::writebacks 43545 # number of writebacks
|
|
system.cpu.icache.writebacks::total 43545 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45588 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 45588 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 45588 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996676500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 996676500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996676500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 996676500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996676500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 996676500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.694130 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.694130 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements 97176 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 31292.341702 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 10980599000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 476.632754 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.083150 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.625798 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.954966 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12834 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17840 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41101 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 41101 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 41101 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 77547 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 41101 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 77547 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4487 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 4487 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 4487 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 128588 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 128588 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269327500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 9269327500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492863000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 492863000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2253034500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2253034500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 492863000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11522362000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 12015225000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 492863000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11522362000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 12015225000 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 39944 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45588 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 45588 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 45588 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 160547 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 206135 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 45588 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 160547 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098425 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098425 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098425 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.623805 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.207219 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.207219 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109842.433697 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109842.433697 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103426.115498 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103426.115498 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 93439.706660 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 93439.706660 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 86552 # number of writebacks
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246157500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246157500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446695500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446695500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029647000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029647000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446695500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275804500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 10722500000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446695500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275804500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 10722500000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 97176 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
|
system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadResp 26198 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 7237 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 102317 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 102317 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 128515 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 128515 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks)
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|
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
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|
|
|
---------- End Simulation Statistics ----------
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