eb0e416998
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar. src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. --HG-- rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
158 lines
4.4 KiB
C++
158 lines
4.4 KiB
C++
/*
|
|
* Copyright (c) 2002-2005 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
* Authors: Nathan Binkert
|
|
* Steve Reinhardt
|
|
*/
|
|
|
|
#include <algorithm>
|
|
#include <map>
|
|
#include <string>
|
|
#include <utility>
|
|
|
|
#include "base/trace.hh"
|
|
#include "config/full_system.hh"
|
|
#include "cpu/base.hh"
|
|
#include "cpu/thread_context.hh"
|
|
#include "cpu/pc_event.hh"
|
|
#include "sim/debug.hh"
|
|
#include "sim/root.hh"
|
|
#include "sim/system.hh"
|
|
|
|
using namespace std;
|
|
|
|
PCEventQueue::PCEventQueue()
|
|
{}
|
|
|
|
PCEventQueue::~PCEventQueue()
|
|
{}
|
|
|
|
bool
|
|
PCEventQueue::remove(PCEvent *event)
|
|
{
|
|
int removed = 0;
|
|
range_t range = equal_range(event);
|
|
for (iterator i = range.first; i != range.second; ++i) {
|
|
if (*i == event) {
|
|
DPRINTF(PCEvent, "PC based event removed at %#x: %s\n",
|
|
event->pc(), event->descr());
|
|
pc_map.erase(i);
|
|
++removed;
|
|
}
|
|
}
|
|
|
|
return removed > 0;
|
|
}
|
|
|
|
bool
|
|
PCEventQueue::schedule(PCEvent *event)
|
|
{
|
|
pc_map.push_back(event);
|
|
sort(pc_map.begin(), pc_map.end(), MapCompare());
|
|
|
|
DPRINTF(PCEvent, "PC based event scheduled for %#x: %s\n",
|
|
event->pc(), event->descr());
|
|
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
PCEventQueue::doService(ThreadContext *tc)
|
|
{
|
|
Addr pc = tc->readPC() & ~0x3;
|
|
int serviced = 0;
|
|
range_t range = equal_range(pc);
|
|
for (iterator i = range.first; i != range.second; ++i) {
|
|
// Make sure that the pc wasn't changed as the side effect of
|
|
// another event. This for example, prevents two invocations
|
|
// of the SkipFuncEvent. Maybe we should have separate PC
|
|
// event queues for each processor?
|
|
if (pc != (tc->readPC() & ~0x3))
|
|
continue;
|
|
|
|
DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n",
|
|
(*i)->pc(), (*i)->descr());
|
|
|
|
(*i)->process(tc);
|
|
++serviced;
|
|
}
|
|
|
|
return serviced > 0;
|
|
}
|
|
|
|
void
|
|
PCEventQueue::dump() const
|
|
{
|
|
const_iterator i = pc_map.begin();
|
|
const_iterator e = pc_map.end();
|
|
|
|
for (; i != e; ++i)
|
|
cprintf("%d: event at %#x: %s\n", curTick, (*i)->pc(),
|
|
(*i)->descr());
|
|
}
|
|
|
|
PCEventQueue::range_t
|
|
PCEventQueue::equal_range(Addr pc)
|
|
{
|
|
return std::equal_range(pc_map.begin(), pc_map.end(), pc, MapCompare());
|
|
}
|
|
|
|
BreakPCEvent::BreakPCEvent(PCEventQueue *q, const std::string &desc, Addr addr,
|
|
bool del)
|
|
: PCEvent(q, desc, addr), remove(del)
|
|
{
|
|
}
|
|
|
|
void
|
|
BreakPCEvent::process(ThreadContext *tc)
|
|
{
|
|
StringWrap name(tc->getCpuPtr()->name() + ".break_event");
|
|
DPRINTFN("break event %s triggered\n", descr());
|
|
debug_break();
|
|
if (remove)
|
|
delete this;
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
extern "C"
|
|
void
|
|
sched_break_pc_sys(System *sys, Addr addr)
|
|
{
|
|
new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
|
|
}
|
|
|
|
extern "C"
|
|
void
|
|
sched_break_pc(Addr addr)
|
|
{
|
|
for (vector<System *>::iterator sysi = System::systemList.begin();
|
|
sysi != System::systemList.end(); ++sysi) {
|
|
sched_break_pc_sys(*sysi, addr);
|
|
}
|
|
|
|
}
|
|
#endif
|