108 lines
4.2 KiB
C++
108 lines
4.2 KiB
C++
/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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#ifndef __SIM_PROBE_MEM_HH__
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#define __SIM_PROBE_MEM_HH__
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#include <memory>
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#include "mem/packet.hh"
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#include "sim/probe/probe.hh"
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namespace ProbePoints {
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/**
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* A struct to hold on to the essential fields from a packet, so that
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* the packet and underlying request can be safely passed on, and
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* consequently modified or even deleted.
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*/
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struct PacketInfo {
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MemCmd cmd;
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Addr addr;
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uint32_t size;
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Request::FlagsType flags;
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Addr pc;
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explicit PacketInfo(const PacketPtr& pkt) :
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cmd(pkt->cmd),
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addr(pkt->getAddr()),
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size(pkt->getSize()),
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flags(pkt->req->getFlags()),
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pc(pkt->req->hasPC() ? pkt->req->getPC() : 0) { }
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};
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/**
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* Packet probe point
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*
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* This probe point provides a unified interface for components that
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* want to instrument Packets in the memory system. Components should
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* when possible adhere to the following naming scheme:
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*
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* <ul>
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*
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* <li>PktRequest: Requests sent out on the memory side of a normal
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* components and incoming requests for memories. Packets should
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* not be duplicated (i.e., a packet should only appear once
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* irrespective of the receiving end requesting a retry).
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*
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* <li>PktResponse: Response received from the memory side of a
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* normal component or a response being sent out from a memory.
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*
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* <li>PktRequestCPU: Incoming, accepted, memory request on the CPU
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* side of a two-sided component. This probe point is primarily
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* intended for components that cache or forward requests (e.g.,
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* caches and XBars), single-sided components should use
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* PktRequest instead. The probe point should only be called
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* when a packet is accepted.
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*
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* <li>PktResponseCPU: Outgoing response memory request on the CPU
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* side of a two-sided component. This probe point is primarily
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* intended for components that cache or forward requests (e.g.,
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* caches and XBars), single-sided components should use
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* PktRequest instead.
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*
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* </ul>
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*
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*/
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typedef ProbePointArg<PacketInfo> Packet;
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typedef std::unique_ptr<Packet> PacketUPtr;
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}
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#endif
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