582 lines
16 KiB
C++
582 lines
16 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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* Steve Reinhardt
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*/
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#include <string>
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#include <vector>
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#include "arch/arm/faults.hh"
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#include "arch/arm/pagetable.hh"
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#include "arch/arm/tlb.hh"
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#include "arch/arm/utility.hh"
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "mem/page_table.hh"
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#include "params/ArmTLB.hh"
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#include "sim/process.hh"
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#if FULL_SYSTEM
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#include "arch/arm/table_walker.hh"
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#endif
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using namespace std;
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using namespace ArmISA;
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TLB::TLB(const Params *p)
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: BaseTLB(p), size(p->size), nlu(0)
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#if FULL_SYSTEM
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, tableWalker(p->walker)
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#endif
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{
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table = new TlbEntry[size];
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memset(table, 0, sizeof(TlbEntry[size]));
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#if FULL_SYSTEM
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tableWalker->setTlb(this);
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#endif
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}
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TLB::~TLB()
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{
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if (table)
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delete [] table;
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}
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TlbEntry*
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TLB::lookup(Addr va, uint8_t cid)
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{
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// XXX This should either turn into a TlbMap or add caching
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TlbEntry *retval = NULL;
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// Do some kind of caching, fast indexing, anything
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int x = 0;
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while (retval == NULL && x < size) {
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if (table[x].match(va, cid)) {
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retval = &table[x];
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if (x == nlu)
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nextnlu();
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break;
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}
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x++;
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}
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DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
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va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
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retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
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retval ? retval->ap : 0);
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;
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return retval;
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}
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// insert a new TLB entry
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void
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TLB::insert(Addr addr, TlbEntry &entry)
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{
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DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
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" asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
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" domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
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entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
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entry.xn, entry.ap, entry.domain);
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if (table[nlu].valid)
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DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
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table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N,
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table[nlu].size, table[nlu].ap);
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// XXX Update caching, lookup table etc
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table[nlu] = entry;
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// XXX Figure out how entries are generally inserted in ARM
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nextnlu();
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}
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void
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TLB::printTlb()
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{
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int x = 0;
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TlbEntry *te;
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DPRINTF(TLB, "Current TLB contents:\n");
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while (x < size) {
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te = &table[x];
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if (te->valid)
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DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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x++;
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}
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}
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void
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TLB::flushAll()
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{
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DPRINTF(TLB, "Flushing all TLB entries\n");
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int x = 0;
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TlbEntry *te;
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while (x < size) {
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te = &table[x];
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if (te->valid)
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DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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x++;
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}
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memset(table, 0, sizeof(TlbEntry[size]));
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nlu = 0;
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}
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void
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TLB::flushMvaAsid(Addr mva, uint64_t asn)
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{
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DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
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TlbEntry *te;
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te = lookup(mva, asn);
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while (te != NULL) {
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DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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te->valid = false;
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te = lookup(mva,asn);
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}
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}
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void
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TLB::flushAsid(uint64_t asn)
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{
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DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
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int x = 0;
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TlbEntry *te;
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while (x < size) {
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te = &table[x];
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if (te->asid == asn) {
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te->valid = false;
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DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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}
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x++;
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}
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}
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void
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TLB::flushMva(Addr mva)
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{
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DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
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int x = 0;
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TlbEntry *te;
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while (x < size) {
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te = &table[x];
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Addr v = te->vpn << te->N;
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if (mva >= v && mva < v + te->size) {
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te->valid = false;
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DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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}
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x++;
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}
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}
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void
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TLB::serialize(ostream &os)
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{
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panic("Implement Serialize\n");
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}
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void
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TLB::unserialize(Checkpoint *cp, const string §ion)
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{
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panic("Need to properly unserialize TLB\n");
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}
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void
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TLB::regStats()
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{
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read_hits
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.name(name() + ".read_hits")
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.desc("DTB read hits")
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;
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read_misses
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.name(name() + ".read_misses")
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.desc("DTB read misses")
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;
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read_accesses
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.name(name() + ".read_accesses")
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.desc("DTB read accesses")
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;
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write_hits
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.name(name() + ".write_hits")
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.desc("DTB write hits")
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;
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write_misses
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.name(name() + ".write_misses")
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.desc("DTB write misses")
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;
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write_accesses
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.name(name() + ".write_accesses")
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.desc("DTB write accesses")
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;
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hits
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.name(name() + ".hits")
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.desc("DTB hits")
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;
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misses
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.name(name() + ".misses")
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.desc("DTB misses")
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;
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accesses
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.name(name() + ".accesses")
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.desc("DTB accesses")
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;
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hits = read_hits + write_hits;
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misses = read_misses + write_misses;
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accesses = read_accesses + write_accesses;
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}
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#if !FULL_SYSTEM
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Fault
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TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
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Translation *translation, bool &delay, bool timing)
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{
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// XXX Cache misc registers and have miscreg write function inv cache
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Addr vaddr = req->getVaddr() & ~PcModeMask;
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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uint32_t flags = req->getFlags();
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bool is_fetch = (mode == Execute);
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bool is_write = (mode == Write);
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if (!is_fetch) {
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assert(flags & MustBeOne);
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if (sctlr.a || !(flags & AllowUnaligned)) {
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if (vaddr & flags & AlignmentMask) {
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return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
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}
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}
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}
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Addr paddr;
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Process *p = tc->getProcessPtr();
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if (!p->pTable->translate(vaddr, paddr))
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return Fault(new GenericPageTableFault(vaddr));
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req->setPaddr(paddr);
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return NoFault;
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}
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#else // FULL_SYSTEM
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Fault
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TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
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{
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return NoFault;
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}
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Fault
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TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
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bool is_write, uint8_t domain, bool sNp)
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{
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return NoFault;
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}
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Fault
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TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
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Translation *translation, bool &delay, bool timing)
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{
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// XXX Cache misc registers and have miscreg write function inv cache
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Addr vaddr = req->getVaddr() & ~PcModeMask;
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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uint32_t flags = req->getFlags();
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bool is_fetch = (mode == Execute);
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bool is_write = (mode == Write);
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bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode);
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DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags
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& UserMode);
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// If this is a clrex instruction, provide a PA of 0 with no fault
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// This will force the monitor to set the tracked address to 0
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// a bit of a hack but this effectively clrears this processors monitor
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if (flags & Request::CLREX){
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req->setPaddr(0);
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req->setFlags(Request::UNCACHEABLE);
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req->setFlags(Request::CLREX);
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return NoFault;
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}
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if ((req->isInstFetch() && (!sctlr.i)) ||
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((!req->isInstFetch()) && (!sctlr.c))){
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req->setFlags(Request::UNCACHEABLE);
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}
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if (!is_fetch) {
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assert(flags & MustBeOne);
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if (sctlr.a || !(flags & AllowUnaligned)) {
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if (vaddr & flags & AlignmentMask) {
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return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
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}
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}
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}
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uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
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Fault fault;
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if (!sctlr.m) {
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req->setPaddr(vaddr);
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if (sctlr.tre == 0) {
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req->setFlags(Request::UNCACHEABLE);
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} else {
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PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
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NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
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if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
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req->setFlags(Request::UNCACHEABLE);
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}
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// Set memory attributes
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TlbEntry temp_te;
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tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
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temp_te.shareable = true;
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DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
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%d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
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temp_te.innerAttrs, temp_te.outerAttrs);
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setAttr(temp_te.attributes);
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return trickBoxCheck(req, mode, 0, false);
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}
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DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id);
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// Translation enabled
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TlbEntry *te = lookup(vaddr, context_id);
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if (te == NULL) {
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if (req->isPrefetch()){
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//if the request is a prefetch don't attempt to fill the TLB
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//or go any further with the memory access
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return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
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}
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// start translation table walk, pass variables rather than
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// re-retreaving in table walker for speed
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DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
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vaddr, context_id);
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fault = tableWalker->walk(req, tc, context_id, mode, translation,
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timing);
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if (timing) {
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delay = true;
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// for timing mode, return and wait for table walk
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return fault;
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}
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if (fault)
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return fault;
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te = lookup(vaddr, context_id);
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if (!te)
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printTlb();
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assert(te);
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}
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// Set memory attributes
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DPRINTF(TLBVerbose,
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"Setting memory attributes: shareable: %d, innerAttrs: %d, \
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outerAttrs: %d\n",
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te->shareable, te->innerAttrs, te->outerAttrs);
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setAttr(te->attributes);
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if (te->nonCacheable)
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req->setFlags(Request::UNCACHEABLE);
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uint32_t dacr = tc->readMiscReg(MISCREG_DACR);
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switch ( (dacr >> (te->domain * 2)) & 0x3) {
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case 0:
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DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
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" write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
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if (is_fetch)
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return new PrefetchAbort(vaddr,
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(te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
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else
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return new DataAbort(vaddr, te->domain, is_write,
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(te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
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case 1:
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// Continue with permissions check
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break;
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case 2:
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panic("UNPRED domain\n");
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case 3:
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req->setPaddr(te->pAddr(vaddr));
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fault = trickBoxCheck(req, mode, te->domain, te->sNp);
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if (fault)
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return fault;
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return NoFault;
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}
|
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|
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uint8_t ap = te->ap;
|
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if (sctlr.afe == 1)
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ap |= 1;
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bool abt;
|
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|
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/* if (!sctlr.xp)
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ap &= 0x3;
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*/
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switch (ap) {
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case 0:
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DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
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if (!sctlr.xp) {
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switch ((int)sctlr.rs) {
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case 2:
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abt = is_write;
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break;
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case 1:
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abt = is_write || !is_priv;
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break;
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case 0:
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case 3:
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default:
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abt = true;
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break;
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}
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} else {
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abt = true;
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}
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break;
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case 1:
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abt = !is_priv;
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break;
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case 2:
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abt = !is_priv && is_write;
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break;
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case 3:
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abt = false;
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break;
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case 4:
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panic("UNPRED premissions\n");
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case 5:
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abt = !is_priv || is_write;
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break;
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case 6:
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case 7:
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abt = is_write;
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break;
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default:
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panic("Unknown permissions\n");
|
|
}
|
|
if ((is_fetch) && (abt || te->xn)) {
|
|
DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
|
|
" write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
|
|
return new PrefetchAbort(vaddr,
|
|
(te->sNp ? ArmFault::Permission0 :
|
|
ArmFault::Permission1));
|
|
} else if (abt) {
|
|
DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
|
|
" write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
|
|
return new DataAbort(vaddr, te->domain, is_write,
|
|
(te->sNp ? ArmFault::Permission0 :
|
|
ArmFault::Permission1));
|
|
}
|
|
|
|
req->setPaddr(te->pAddr(vaddr));
|
|
// Check for a trickbox generated address fault
|
|
fault = trickBoxCheck(req, mode, te->domain, te->sNp);
|
|
if (fault)
|
|
return fault;
|
|
|
|
return NoFault;
|
|
}
|
|
|
|
#endif
|
|
|
|
Fault
|
|
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
|
|
{
|
|
bool delay = false;
|
|
Fault fault;
|
|
#if FULL_SYSTEM
|
|
fault = translateFs(req, tc, mode, NULL, delay, false);
|
|
#else
|
|
fault = translateSe(req, tc, mode, NULL, delay, false);
|
|
#endif
|
|
assert(!delay);
|
|
return fault;
|
|
}
|
|
|
|
Fault
|
|
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
|
|
Translation *translation, Mode mode)
|
|
{
|
|
assert(translation);
|
|
bool delay = false;
|
|
Fault fault;
|
|
#if FULL_SYSTEM
|
|
fault = translateFs(req, tc, mode, translation, delay, true);
|
|
#else
|
|
fault = translateSe(req, tc, mode, translation, delay, true);
|
|
#endif
|
|
if (!delay)
|
|
translation->finish(fault, req, tc, mode);
|
|
return fault;
|
|
}
|
|
|
|
ArmISA::TLB *
|
|
ArmTLBParams::create()
|
|
{
|
|
return new ArmISA::TLB(this);
|
|
}
|