8e9d44477c
dev/sinic.cc:
- Size the virtualRegs array based on the configured value
- Add debugging stuff for uniquely identifying vnic usage
- Only count totally unprocessed packets when notifying via RxDone
- Add initial virtual address support
- Fix some bugs in accessing packets out of order to make sure that
busy packets are processed first
- Add fifo watermark stuff
- Make number of vnics, zero/delay copy and watermarks parameters
dev/sinic.hh:
add rxUnique and txUnique to uniquely identify tx and rx VNICs
Create a separate list of Busy VNICs since more than one might
be busy and we want to service those first
Add more watermark stuff and new parameters
dev/sinicreg.hh:
Make the number of virtual nics a read-only parameter
add bits for ZeroCopy/DelayCopy
rename Virtual to Vaddr so it's not ambiguous
Add a flag for TxData/RxData to indicate a virtual address
Report rxfifo status in RxDone
python/m5/objects/Ethernet.py:
add more options for the fifo thresholds
add number of vnics as a parameter
add copy type as a parameter
add virtual addressing as a parameter
--HG--
extra : convert_revision : 850e2433b585d65469d4c5d85ad7ca820db10f4a
119 lines
4.8 KiB
Python
119 lines
4.8 KiB
Python
from m5 import *
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from Device import DmaDevice
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from Pci import PciDevice
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class EtherInt(SimObject):
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type = 'EtherInt'
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abstract = True
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peer = Param.EtherInt(NULL, "peer interface")
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class EtherLink(SimObject):
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type = 'EtherLink'
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int1 = Param.EtherInt("interface 1")
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int2 = Param.EtherInt("interface 2")
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delay = Param.Latency('0us', "packet transmit delay")
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delay_var = Param.Latency('0ns', "packet transmit delay variability")
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speed = Param.NetworkBandwidth('1Gbps', "link speed")
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dump = Param.EtherDump(NULL, "dump object")
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class EtherBus(SimObject):
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type = 'EtherBus'
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loopback = Param.Bool(True, "send packet back to the sending interface")
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dump = Param.EtherDump(NULL, "dump object")
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speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
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class EtherTap(EtherInt):
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type = 'EtherTap'
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bufsz = Param.Int(10000, "tap buffer size")
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dump = Param.EtherDump(NULL, "dump object")
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port = Param.UInt16(3500, "tap port")
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class EtherDump(SimObject):
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type = 'EtherDump'
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file = Param.String("dump file")
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maxlen = Param.Int(96, "max portion of packet data to dump")
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if build_env['ALPHA_TLASER']:
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class EtherDev(DmaDevice):
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type = 'EtherDev'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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intr_delay = Param.Latency('0us', "Interrupt Delay")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
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tlaser = Param.Turbolaser(Parent.any, "Turbolaser")
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class EtherDevInt(EtherInt):
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type = 'EtherDevInt'
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device = Param.EtherDev("Ethernet device of this interface")
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class EtherDevBase(PciDevice):
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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clock = Param.Clock('0ns', "State machine processor frequency")
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physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
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hier = Param.HierParams(Parent.any, "Hierarchy global variables")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
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tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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intr_delay = Param.Latency('10us', "Interrupt propagation delay")
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rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
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tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
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rss = Param.Bool(False, "Receive Side Scaling")
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class NSGigE(EtherDevBase):
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type = 'NSGigE'
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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class NSGigEInt(EtherInt):
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type = 'NSGigEInt'
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device = Param.NSGigE("Ethernet device of this interface")
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class Sinic(EtherDevBase):
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type = 'Sinic'
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rx_max_copy = Param.MemorySize('1514B', "rx max copy")
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tx_max_copy = Param.MemorySize('16kB', "tx max copy")
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rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
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rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
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rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
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tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
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tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
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virtual_count = Param.UInt32(1, "Virtualized SINIC")
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zero_copy = Param.Bool(False, "Zero copy receive")
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delay_copy = Param.Bool(False, "Delayed copy transmit")
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virtual_addr = Param.Bool(False, "Virtual addressing")
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class SinicInt(EtherInt):
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type = 'SinicInt'
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device = Param.Sinic("Ethernet device of this interface")
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